Memory system with error detection and retry modes of operation

1. An electrically erasable programmable memory device comprising:

a first receiver to receive a write command and a first error detection code from a controller;

a plurality of second receivers to receive write data and a second error detection code from a controller, the second error detection code encoded by the controller in connection with the write data, wherein the plurality of second receivers are operable to receive the write data in accordance with one of a plurality of modes, a first mode including data comprising symbols respectively transferred on rising and falling edges per clock cycle of a clock signal, and a second mode including data transferred with one symbol per clock cycle; and

a logic circuit, coupled to the plurality of receivers, to determine, using the second error detection code, if the received write data contains at least one error; and

wherein the memory device is to

also detect existence of an error in the write command using the first error detection code,

signal to the controller existence of at least one of error in the write command or error in the write data using a link independent of a link used to receive the write data, and

re-receive the write data from the controller in the event that the logic circuit determines that the received write data contains the at least one error; and

wherein the plurality of second receivers are to receive the write data using the first mode and re-receive the write data using the second mode.

2. The memory device of claim 1 , wherein each error detection code received from the controller is a cyclic code.

3. The memory device of claim 2 , wherein the memory device is further to block execution of the write command in the event of the error in the write command.

4. The memory device of claim 1 , wherein, in the event that the logic circuit determines that the received write data contains the at least one error, the memory device is to perform a retry remedial action that includes re-receiving a write command corresponding to the re-received write data.

5. The memory device of claim 4 , wherein the re-received write command is to have error protection provided by an error correction code.

6. The memory device of claim 1 , wherein the plurality of second receivers comprises a third receiver to receive the write data via a data link, and a fourth receiver to receive the second error detection code via a retry signal link.

7. The memory device of claim 1 , further comprising a buffer to store the write data until a retry remedial action is completed in the event that the logic circuit determines that the received write data contains the at least one error.

8. The memory device of claim 1 , wherein, in the event that the logic circuit determines that the received write data contains the at least one error, the memory device is to perform a retry remedial action that includes at least one of:

re-receiving the write data re-transmitted by the controller with blanks attached; and

re-receiving the write data re-transmitted by the controller using a larger voltage swing than the voltage swing used when first received at the plurality of receivers.

9. The memory device of claim 1 , wherein the memory device is to delay command operations to a location in the memory device corresponding to the respective write data until a retry remedial action is completed in the event that the logic circuit determines that the received write data contains the at least one error.

10. The memory device of claim 1 , embodied as a single chip memory device.

11. The memory device of claim 1 , comprising a plurality of components to instantiate the plurality of receivers and the logic circuit.

12. A method of operation in an electrically erasable programmable memory device, the method comprising:

receiving with a first receiver a write command and a first error detection code from a controller;

receiving with a plurality of second receivers write data and an error detection code from a controller, the second error detection code encoded by the controller using the write data, the write data being received in accordance with one of a plurality of modes, a first mode including data comprising symbols respectively transferred on rising and falling edges per clock cycle of a clock signal, and a second mode including data transferred with one symbol per clock cycle;

determining, using a logic circuit coupled to the plurality of second receivers and using the second error detection code, if the received write data contains at least one error;

signaling an error condition to the controller in connection with the at least one error; and

detecting existence of an error in the write command using the first error detection code;

wherein the method further comprises

also detecting existence of an error in the write command using the first error detection code,

signaling to the controller existence of at least one of error in the write command or error in the write data using a link independent of a link used to receive the write data,

re-receiving the write data from the controller in the event that the logic circuit determines that the received write data contains the at least one error; and

wherein receiving the write data is performed with the plurality of second receivers using the first mode and re-receiving the write data is performed with the plurality of second receivers using the second mode.

13. The method of claim 12 , wherein re-receiving the write data is a part of a retry remedial action in the event of the error condition, the retry remedial action comprises re-receiving the write data re-transmitted by the controller using a larger voltage swing than the voltage swing used when first received at the plurality of second receivers.

14. The method of claim 12 , further comprising re-receiving a write command corresponding to the re-received write data in the event of the at least one error.

15. The method of claim 14 , wherein re-receiving the write command includes receiving an error correction code to protect the re-received write command.

16. The method of claim 12 , wherein re-receiving further comprises re-receiving the write data re-transmitted by the controller with blanks attached.

17. The method of claim 12 , further comprising performing a serial-to-parallel conversion on the write data and the second error detection code.

18. The method of claim 12 , further comprising delaying command operations to a location in the memory device corresponding to the respective write data until the retry remedial action is completed.

19. The method of claim 12 , wherein the method further comprises blocking execution of the write command in the event of the error in the write command.

20. An electrically erasable programmable memory device comprising:

a first receiver to receive a write command and a first error detection code from a controller;

a plurality of second receivers to receive write data and a second error detection code from a controller, the second error detection code encoded by the controller in connection with the write data, wherein the means for receiving the write data and the second error detection code is to receive the write data in accordance with one of a plurality of modes, a first mode including data comprising symbols respectively transferred on rising and falling edges per clock cycle of a clock signal, and a second mode including data transferred with one symbol per clock cycle; and

means, coupled to said plurality of second receivers, for determining, using the second error detection code, if the received write data contains at least one error;

wherein the memory device is to

also detect existence of an error in the write command using the first error detection code,

signal to the controller existence of at least one of error in the write command or error in the write data using a link independent of a link used to receive the write data, and

re-receive the write data from the controller in the event that the logic circuit determines that the received write data contains the at least one error; and

wherein the plurality of second receivers are to receive the write data using the first mode and re-receive the write data using the second mode.

21. The memory device of claim 20 , wherein the memory device is further to block execution of the write command in the event of the error in the write command.