Memory device with retransmission upon error
A controller includes a link interface that is to couple to a first link to communicate bidirectional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
1. A solid state memory device comprising:
a link interface configurable to transfer bidirectional signals in a first configuration, and to transfer unidirectional signals in a second configuration, wherein the link interface includes:
receiver circuitry to receive command information that specifies a read operation of a group of read data bits, and first error detection information associated with the command information, from a controller device; and
transmit circuitry to transmit the group of read data bits, the group of read data bits being transmitted time multiplexed with second error-detection information; and,
an encoder to generate the second error-detection information from the group of read data bits, wherein the transmit circuitry is operable to retransmit the group of read data bits and the second error detection information in the event that an error condition associated with the group of read data bits is detected.
2. The solid state memory device of claim 1 , wherein the second error-detection information is to include a cyclic redundancy check (CRC) code.
3. The solid state memory device of claim 1 , wherein the command information includes address bits that identify a location of the group of read data bits in a memory.
4. The solid state memory device of claim 1 , further comprising:
a circuit to receive remedial action instructions from the controller device in the event that the error condition is detected, wherein the remedial action is to include the receiver circuitry re-receiving the command information associated with the group of read data bits in the event that the error condition is detected.
5. The solid state memory device of claim 4 , wherein the receiver circuitry is to re-receive the command information along with fourth error detection information in the event that the error condition is detected.
6. The solid state memory device of claim 4 , wherein the receiver circuitry is to re-receive the command information using one symbol per clock cycle of a clock signal action in the event that the error condition is detected.
7. The solid state memory device of claim 1 , wherein, in the first configuration, the link interface is configurable as bidirectional for data signals and unidirectional for error detection information and, in the second configuration, is reconfigurable as unidirectional for both data signals and the first error detection information.
8. The solid state memory device of claim 1 , wherein the transmitter circuitry transmits the group of read data bits in a single data rate format.
9. The solid state memory device of claim 1 , wherein transmitter circuitry transmits the group of read data bits using both rising and falling edges of a clock signal.
10. A method of operation of a solid state memory device, the method comprising:
configuring a link interface to transfer signals in one of a bidirectional format in a first configuration, and a unidirectional format in a second configuration;
in one of the first configuration and the second configuration, receiving, from a controller device, command information and first error detection information associated with the command information and transmitting a group of read data bits in response to the command information, the group of read data bits being transmitted time multiplexed with second error-detection information;
prior to transmitting, generating the second error-detection information from the group of read data bits; and
retransmitting the group of read data bits and the second error detection information in the event that an error condition associated with the group of read data bits is detected.
11. The method of claim 10 , wherein the second error-detection information includes a cyclic redundancy check (CRC) code.
12. The method of claim 10 , further comprising:
receiving remedial action instructions from the controller device in the event that the error condition is detected.
13. The method of claim 12 , wherein the remedial action includes re-receiving the command information associated with the group of read data bits in the event that error condition is detected.
14. The method of claim 13 , wherein re-receiving the command information comprises re-receiving the command information along with fourth error detection information action in the event that the error condition is detected.
15. The method of claim 13 , wherein re-receiving the command information comprises re-receiving the command information using one symbol per clock cycle of a clock signal action in the event that the error condition is detected.
16. The method of claim 10 , wherein transmitting the group of read data bits comprises one of transmitting the group of read data bits in a single data rate format, and transmitting the group of read data bits using both rising and falling edges of a clock signal.
17. The method of claim 10 , wherein, in the first configuration, the command information is transmitted using a unidirectional format and data is transferred in a bidirectional format, the data including the plurality of read data bits.
18. The method of claim 17 , wherein, in the second configuration, the command information is received using the unidirectional format and the transmitting of the group of read data bits comprises transmitting the group of read data bits in the unidirectional format.
19. The method of claim 17 , further comprising:
in the first configuration, receiving write data in the bidirectional format, wherein the data includes the write data, and,
receiving, using the unidirectional format, a write command associated with the write data.
20. A solid state memory device comprising:
means for configuring a link interface to transfer signals in one of a bidirectional format in a first configuration, and a unidirectional format in a second configuration;
in one of the first configuration and second configuration, means for receiving, from a controller device, command information and first error detection information associated with the command information, and means for transmitting a group of read data bits in response to the command information, the group of read data bits being transmitted time multiplexed with second error-detection information; and
means for generating the second error-detection information from the group of read data bits; and
wherein the means for transmitting the group of read data bits is to retransmit the group of read data bits and the second error detection information in the event that an error condition associated with the group of read data bits is detected.