On-die termination of address and command signals
A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a value for enabling application of a clock (CK) ODT impedance value to third inputs that receive the CK signal.
1. A memory controller to control a plurality of dynamic random access memory devices (DRAMs), wherein the DRAMs each have address and control inputs (RQ) inputs, and a control pin, configured to be connected to signal lines of an address and control (RQ) bus;
an interface to provide address and control signals to the RQ inputs of the DRAMs;
the memory controller to store register values, in the DRAMs, that specify termination impedance values to apply to the RQ inputs, wherein a first logic level applied to the control pin of a respective DRAM of the DRAMs is to select a first termination value to apply to the RQ inputs of the respective DRAM, and a second logic level applied to the control pin of the respective DRAM is to select a second termination value to apply to the RQ inputs of the respective DRAM.
2. The memory controller of claim 1 , wherein the control pin of each of the DRAMs is tied to one of a first and second voltage level, wherein the first voltage level provides the first logic level and the second voltage level provides the second logic level.
3. The memory controller of claim 1 , each control pin of the DRAMs is to select, for the termination impedance values, between a nominal value stored in a first register and an alternate level stored in a second register, wherein the first logic level is to select the first termination value from the first register and the second logic level is to select the second termination value from the second register.
4. The memory controller of claim 1 , further comprising a driver to provide a clock signal to the DRAMs, wherein the register values include a register value that specifies a termination value to apply to inputs of the DRAMs that receive the clock signal.
5. The memory controller of claim 1 , wherein the interface further comprises a driver to provide a chip select signal to the DRAMs, wherein the register values include a register value that specifies a termination value to apply to inputs of the DRAMs that receive the chip select signal.
6. The memory controller of claim 1 , wherein:
the memory controller is configured to be connected to the plurality of dynamic random access memory devices arranged in a fly-by topology via the address and control (RQ) bus; and
the memory controller is configured to selectively enable on-die termination (ODT) circuitry in one or more of the plurality of dynamic random access memory devices.
7. The memory controller of claim 6 , wherein the on-die termination (ODT) circuitry of a respective memory device of the plurality of dynamic random access memory devices is connected to the RQ inputs of the respective memory device, and the memory controller is configured to dynamically change an operational state of the on-die termination (ODT) circuitry connected to the RQ inputs of the respective memory device of the plurality of dynamic random access memory devices in accordance with memory operations performed by the memory controller.
8. The memory controller of claim 6 , wherein the memory controller is configured to enable termination of the RQ inputs of only the memory device of the plurality of dynamic random access memory devices farthest, on the address and control (RQ) bus, from the memory controller.
9. The memory controller of claim 6 , wherein:
each respective memory device of the plurality of dynamic random access memory devices includes a respective first register that stores a respective first termination value specifying a respective first impedance termination value to apply to the RQ inputs of the respective memory device, and a respective second register that stores a respective second termination value specifying a respective second impedance termination value to apply to the RQ inputs of the respective memory device; and
the memory controller is configured to send, to each respective memory device of the plurality of dynamic random access memory devices, register values for storage in the respective first register and respective second register of the respective memory device, including the respective first termination value specifying the respective first impedance termination value to apply to the RQ inputs of the respective memory device, and the respective second termination value specifying the respective second impedance termination value to apply to the RQ inputs of the respective memory device.
10. The memory controller of claim 9 , wherein:
each respective memory device of the plurality of dynamic random access memory devices includes a respective third register that stores a value used to specify, as a nominal impedance to be used for termination of the RQ inputs of the respective memory device, either the respective first impedance termination value or the respective second impedance termination value; and
the memory controller is configured to store a respective value in the respective third register of a respective memory device of the plurality of dynamic random access memory devices.
11. A method of operating a memory controller to control operation of a dynamic random access memory device (DRAM) having a first register and second register, wherein:
the memory controller is connected to the DRAM by an address and control (RQ) bus;
the DRAM has a control pin, RQ inputs, configured to be connected to signal lines of the address and control (RQ) bus, and on-die termination (ODT) circuitry connected to the RQ inputs;
the first register of the DRAM stores a first termination value specifying a first impedance termination value to apply to the RQ inputs, and the second register of the DRAM stores a second termination value specifying a second impedance termination value to apply to the RQ inputs; and
the method includes the memory controller asserting a first logic level on the control pin of the DRAM to select the first termination value from the first register so as to apply the first impedance termination value to the RQ inputs of the DRAM, and asserting a second logic level on the control pin of the DRAM to select the second termination value from the second register so as to apply the second impedance termination value to the RQ inputs of the DRAM.
12. The method of claim 11 , wherein the DRAM has a third register that stores a value used to specify, as a nominal impedance to be used for termination of the RQ inputs, either the first impedance termination value or the second impedance termination value, and the method includes the memory controller storing a respective value in the third register of the DRAM.
13. The method of claim 11 , including the memory controller storing the first termination value in the first register of the DRAM and storing the second termination value in the second register of the DRAM.
14. The method of claim 11 , wherein the control pin of the DRAM comprises a first control pin, the DRAM includes a second control pin, and the method includes the memory controller asserting a respective logic level on the second control pin that, in combination with the memory controller asserting a predefined logic level on the first control pin, causes the DRAM to apply a third impedance termination value to the RQ inputs of the DRAM.
15. The method of claim 11 , wherein the control pin of the DRAM comprises a first control pin, the DRAM includes a second control pin, and the method includes the memory controller selectively enabling and disabling operation of the on-die termination (ODT) circuitry connected to the RQ inputs by asserting a respective control value on the second control pin.
16. The method of claim 11 , wherein:
the memory controller is configured to be connected to a plurality of memory devices arranged in a fly-by topology via the address and control (RQ) bus;
the plurality of memory devices include the DRAM;
the plurality of memory devices each include RQ inputs, configured to be connected to signal lines of the address and control (RQ) bus, and on-die termination (ODT) circuitry connected to the RQ inputs; and
the method includes the memory controller selectively enabling the ODT circuitry in one or more of the plurality of memory devices.
17. The method of claim 16 , including the memory controller dynamically changing an operational state of the on-die termination (ODT) circuitry connected to the RQ inputs of a respective memory device of the plurality of memory devices in accordance with memory operations performed by the memory controller.
18. The method of claim 16 , including the memory controller enabling termination of the RQ inputs of only the memory device of the plurality of memory devices farthest, on the address and control (RQ) bus, from the memory controller.
19. The method of claim 16 , wherein:
each respective memory device of the plurality of memory devices includes a respective first register that stores a respective first termination value specifying a respective first impedance termination value to apply to the RQ inputs of the respective memory device, and a respective second register that stores a respective second termination value specifying a respective second impedance termination value to apply to the RQ inputs of the respective memory device; and
the method includes the memory controller sending, to each respective memory device of the plurality of memory devices, register values for storage in the respective first register and respective second register of the respective memory device, including the respective first termination value specifying the respective first impedance termination value to apply to the RQ inputs of the respective memory device, and the respective second termination value specifying the respective second impedance termination value to apply to the RQ inputs of the respective memory device.
20. A memory controller to control the operation of a plurality of memory devices including a first memory device and a second memory device, each memory device having command/address inputs to receive command and address signals, and a control pin to select between a first termination value and a second termination value to apply to the command/address inputs, the memory controller comprising:
a command/address interface to transmit command/address signals to the command/address inputs of the plurality of memory devices;
the memory controller to store register values, in the plurality of memory devices, that specify termination impedance values to apply to the command/address inputs, such that:
the first memory device selects a first termination impedance value to apply to the command/address inputs based on application of a first voltage to the control pin of the first memory device, and
the second memory device selects a second termination impedance value to apply to the command/address inputs based on application of a second voltage to the control pin of the second memory device, wherein the second termination impedance value is different from the first termination impedance value and the second voltage is different from the first voltage.