On die termination circuit
The present invention discloses an on die termination circuit. The on die termination circuit used in a DDR2 employs transmission gates as pull-up and pull-down switches, equalizes pull-up and pull-down resistance values by changing connection relations between switches and resistors, and maintains a constant voltage of an input pin.
1. An on die termination circuit, comprising:
an input transmission line for transmitting a data of an external input pin to an input buffer;
a first resistor connected to a first voltage source;
a first transmission gate connected between the first resistor and the input transmission line and driven according to a first termination signal and an inverted first termination signal;
a second resistor connected to a second voltage source;
a second transmission gate connected between the second resistor and the input transmission line and driven according to the first termination signal and the inverted first termination signal;
a third resistor connected to the first voltage source;
a third transmission gate connected between the third resistor and the input transmission line and driven according to a second termination signal and an inverted second termination signal;
a fourth resistor connected to the second voltage source; and
a fourth transmission gate connected between the fourth resistor and the input transmission line and driven according to the second termination signal and the inverted second termination signal.
2. The circuit of claim 1 , wherein the first to fourth transmission gates are transmission gates in which NMOS and PMOS transistors are connected in parallel and operated within a voltage range of−Vtp to VDD−Vtn.
3. The circuit of claim 1 , wherein the first and second resistors use the same resistance value, the third and fourth resistors use the same resistance value, the first voltage source is VDD, and the second voltage source is VSS.
4. An on die termination circuit, comprising:
an input transmission line for transmitting a data of an external input pin to an input buffer;
a first resistor connected to a first voltage source;
a first transmission gate connected between the first resistor and the input transmission line and driven according to a first termination signal;
a second transmission gate connected between the second resistor and the input transmission line and driven according to the first termination signal wherein a turn-on resistance of the first transmission gate is equal to that of the second transmission gate;
a second resistor connected to a second voltage source;
a third resistor connected to the first voltage source;
a third transmission gate connected between the third resistor and the input transmission line and driven according to a second termination signal;
a fourth resistor connected to the second voltage source; and
a fourth transmission gate connected between the fourth resistor and the input transmission line and driven according to the second termination signal, wherein a turn-on resistance of the third transmission gate is equal to that of the fourth transmission gate.
5. The circuit of claim 4 , wherein the first to fourth transmission gates are transmission gates in which NMOS and PMOS transistors are connected in parallel and operated within a voltage range of−Vtp to VDD−Vtn.
6. The circuit of claim 4 , wherein the first and second resistors use the same resistance value, the third and fourth resistors use the same resistance value, the first voltage source is VDD, and the second voltage source is VSS.