Unidirectional error code transfer method for a bidirectional data link
A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
1. A method of operating a controller, comprising:
transmitting write data;
receiving first error-detection information corresponding to at least a portion of the write data; and
detecting errors in at least the portion of the write data based on both the first error-detection information and a delayed version of second error-detection information corresponding to the write data, and, if an error is detected, asserting an error condition.
2. The method of claim 1 , further comprising:
at the controller,
dynamically generating the second error-detection information for at least the portion of the write data; and
detecting errors in at least the portion of the write data based on the first error-detection information and a delayed version of the second error-detection information.
3. The method of claim 2 , further comprising:
dynamically generating the second error-detection information using a cyclic redundancy code (CRC).
4. The method of claim 1 , further comprising adjusting a timing of the first error-detection information relative to transmission of the first write data.
5. The method of claim 1 , further comprising performing a remedial action if the error condition is asserted.
6. The method of claim 5 , wherein the remedial action includes re-transmitting the write data.
7. The method of claim 1 , further comprising:
dynamically generating error-detection information for a group of the outgoing write data; and
detecting errors in at least the portion of the write data based on the dynamically generated error-detection information for the group and a return from a remote device of error information corresponding to the group of the write data as received at the remote device.
8. The method of claim 1 , further comprising:
at the controller,
receiving read data;
receiving third error-detection information corresponding to at least a portion of the read data;
dynamically generating fourth error-detection information for at least a portion of the read data; and
detecting errors in at least the portion of the read data based on the third error-detection information and the fourth error-detection information, and, if an error is detected, asserting an error condition.
9. The method of claim 8 , further comprising comparing the third error-detection information with the fourth error-detection information to detect errors in at least the portion of the read data.
10. The method of claim 9 , further comprising performing a remedial action if the error condition is asserted.
11. The method of claim 10 , wherein the remedial action includes re-transmitting the read data.
12. The method of claim 8 , further comprising dynamically generating fourth error-detection information using a cyclic redundancy code (CRC).
13. The method of claim 8 , further comprising:
dynamically generating error-detection information for a group of the incoming read data; and
detecting errors in at least the portion of the read data based on the dynamically generating error-detection information for the group and a return of corresponding error information from a remote device corresponding to the group of the read data, wherein the read data is received from the remote device.
14. A controller comprising:
a transmitter circuit to transmit write data;
a receiver circuit to receive first error-detection information corresponding to at least a portion of the write data; and
an error detection logic circuit to detect errors in at least the portion of the write data based on both the first error-detection information and a delayed version of second error-detection information corresponding to the write data.
15. The controller of claim 14 , further comprising:
an encoder to dynamically generate the second error-detection information for at least the portion of the write data; and
a delay circuit to delay the second error-detection information, wherein
the error detection logic circuit is to detect errors in at least the portion of the write data based on the first error-detection information and the delayed second error-detection information.
16. The controller of claim 15 , wherein the encoder is to dynamically generate the second error-detection information using a cyclic redundancy code (CRC).
17. The controller of claim 14 , further comprising a synchronization circuit to adjust a timing of the first error-detection information relative to transmission of the first write data.
18. The controller of claim 14 , further comprising a retry logic circuit to perform a remedial action if the error condition is asserted.
19. The controller of claim 18 , wherein the retry logic circuit is to re-transmit the write data.
20. The controller of claim 15 , wherein
the encoder is further to dynamically generate error-detection information for a group of the outgoing write data;
the receiver circuit is further to receive a return from a remote device of error information corresponding to the group of the write data as received at the remote device; and
the error detection logic circuit is further to detect errors in at least the portion of the write data based on the dynamically generated error-detection information for the group and the return of the corresponding error information.
21. The controller of claim 15 , wherein
the receiver circuit is further to receive read data and third error-detection information corresponding to at least a portion of the read data;
the encoder is further to dynamically generate fourth error-detection information for at least a portion of the read data; and
the error detection logic circuit is further to detect errors in at least the portion of the read data based on the third error-detection information and the fourth error-detection information.
22. The controller of claim 21 , wherein the error detection logic circuit is to compare the third error-detection information with the fourth error-detection information to detect errors in at least the portion of the read data.
23. The controller of claim 22 , further comprising a retry logic circuit to perform a remedial action if the error condition is asserted.
24. The controller of claim 23 , wherein the retry logic circuit is to re-transmit the read data.
25. The controller of claim 21 , wherein encoder is to dynamically generate the fourth error-detection information using a cyclic redundancy code (CRC).
26. The controller of claim 21 , wherein
the error detection logic circuit is further to dynamically generate error-detection information for a group of the incoming read data;
the receiver circuit is further to receive a return from a remote device of error information corresponding to the group of the read data; and
the error detection logic circuit is further to detect errors in at least the portion of the read data based on the dynamically generated error-detection information for the group and the return of corresponding error information.
27. The controller of claim 14 , wherein the memory controller is a memory controller to be coupled to a memory device.
28. The controller of claim 14 , wherein the memory controller is implemented in a single integrated circuit.
29. A controller comprising:
means for transmitting write data;
means for receiving first error-detection information corresponding to at least a portion of the write data; and
means for detecting errors in at least the portion of the write data, based on both the first error-detection information and a delayed version of second error-detection information corresponding to the write data.