High-speed signaling systems with adaptable pre-emphasis and equalization
A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
1. An integrated circuit (IC), comprising:
driver circuitry to transmit a digital bit stream to a receiving IC over a signal path; and
equalizer circuitry including a set of at least three taps to equalize the digital bit stream in response to respective bits of the digital bit stream, the equalizer circuitry having multiple modes, wherein
in a first mode of the multiple modes, the digital bit stream is equalized using the equalization circuitry to compensate for pre-tap interference, current-tap interference, and post-tap interference, and
in a second mode of the multiple modes, the digital bit stream is equalized using the equalization circuitry to compensate for current-tap interference and pre-tap interference but not post-tap interference.
2. The IC of claim 1 , wherein:
the IC is configured to enter the first mode or the second mode in response to setting information received from the receiving IC.
3. The IC of claim 2 , wherein:
the setting information being based on a quality measurement of the digital bit stream.
4. The IC of claim 3 , wherein:
the quality measurement comprises a bit error rate (BER).
5. The IC of claim 2 , wherein:
the setting information is received over a backchannel.
6. The IC of claim 5 , wherein:
the backchannel comprises a communication path other than the signaling path.
7. An integrated circuit (IC) chip, comprising:
a driver to transmit a digital bit stream to a second IC chip over a signal path;
circuitry to equalize the digital bit stream, the circuitry having a pre-tap, a main tap, and a post-tap;
wherein the IC chip has at least two equalization modes, including
a first mode that utilizes the main tap, the pre-tap, and the post-tap, where the pre-tap compensates for pre-tap interference, and the post-tap compensates for post-tap interference; and
a second mode where only the main tap and the pre-tap are used to equalize the digital bit stream.
8. The IC chip of claim 7 , wherein a selection between the first mode and the second mode is made based on feedback provided by the second IC chip.
9. The IC chip of claim 8 , further comprising:
a receiver circuit to receive the feedback from the second IC chip via a backchannel.
10. The IC chip of claim 7 , wherein a selection between the first mode and the second mode is made based on a quality measurement of the digital bit stream.
11. The IC chip of claim 10 , wherein the IC chip is to receive from the second IC chip the quality measurement, and is to automatically configure the first mode or the second mode in response to the quality measurement.
12. The IC chip of claim 11 , wherein the quality measurement comprises an error rate indicator.
13. The IC chip of claim 7 , wherein the post-tap is disabled in the second mode.
14. A method of transmitting a digital bit stream from a first integrated circuit (IC) chip to a second IC chip over a signal path, comprising:
equalizing the digital bit stream using circuitry having a pre-tap, a main tap, and a post-tap, the equalizing performed according to an equalization mode;
wherein if the equalization mode is a first equalization mode, the equalizing involves utilizing the main tap, the pre-tap, and the post-tap, where the pre-tap compensates for pre-tap interference, and the post-tap compensates for post-tap interference; and
wherein if the equalization mode is a second equalization mode, the equalizing involves utilizing only the main tap and the pre-tap to equalize the digital bit stream.
15. The method according to claim 14 , further comprising:
selecting between the first mode and the second mode based on feedback generated by the second IC chip.
16. The method according to claim 15 , further comprising:
receiving the feedback from the second IC chip via a backchannel.
17. The method according to claim 14 , further comprising:
selecting between the first mode and the second mode based on a quality measurement of the digital bit stream.
18. The method according to claim 17 , further comprising:
receiving the quality measurement from the second IC chip; and
automatically configuring the first mode or the second mode in response to the quality measurement.
19. The method according to claim 17 , wherein the quality measurement comprises an error rate indicator.
20. The method according to claim 14 , further comprising:
disabling the post-tap in the second equalization mode.