Memory cell and method for fabricating same

1. A method for fabricating a memory cell, comprising:

forming a stacked insulating layer, and a lower conductive layer on a semiconductor substrate;

patterning the lower conductive layer and the insulating layer to form a gap region;

forming a gate insulating layer on exposed surfaces of the semiconductor substrate and the lower conductive layer in the gap region;

forming a gate pattern on the gate insulating layer for filling the gap region, the gate pattern protruded upward to have sidewall portions exposed above the lower conductive layer;

forming an upper sidewall pattern on each exposed sidewall portion of the gate pattern;

patterning the lower conductive layer and the insulating layer to form a lower sidewall pattern and a charge storage layer under each upper sidewall pattern, wherein the gate pattern and each upper sidewall pattern are used as an etching mask; and

forming a source region and a drain region in the semiconductor substrate.

2. The method as recited in claim 1 , further comprising doping impurities into an exposed portion of the semiconductor substrate in the gap region to form a channel region.

3. The method as recited in claim 1 , wherein forming the gate pattern comprises:

forming a mask layer on the lower conductive layer;

patterning the mask layer to form the gap region;

forming a gate pattern on the gate oxide layer for filling the gap region; and

removing the mask layer to expose sidewall portions of the gate pattern.

4. The method as recited in claim 1 , wherein forming the gate pattern comprises:

stacking an interlayer insulating layer and a mask layer on the lower conductive layer;

patterning the mask layer and interlayer insulating layer to form the gap region;

forming a gate pattern on the gate oxide layer for filling the gap region; and

removing the mask layer to expose the interlayer insulating layer and sidewall portions of the gate pattern.

5. The method as recited in claim 1 , wherein forming the upper sidewall pattern on each exposed sidewall portion comprises:

forming an upper conductive layer on the semiconductor substrate; and

anisotropically etching the upper conductive layer to expose the lower conductive layer.

6. The method as recited in claim 1 , wherein the stacked insulating layer includes a tunnel oxide layer, a charge trapping layer and blocking insulating layer.

7. The method as recited in claim 1 , wherein the gate insulating layer is formed at a thickness having an equivalent oxide thickness less than an equivalent oxide thickness of the stacked insulating layer.

8. A method for fabricating a memory cell, comprising:

stacking an insulating layer, a lower conductive layer and a mask layer on a semiconductor substrate;

patterning the mask layer, the lower conductive layer and the insulating layer to form a gap region;

forming a gate oxide layer on exposed surfaces of the semiconductor substrate and the lower conductive layer in the gap region;

forming a gate pattern on the gate oxide layer for filling the gap region;

removing the mask layer to expose sidewall portions of the gate pattern;

forming an upper sidewall pattern on each exposed sidewall portion of the gate pattern;

patterning the lower conductive layer and the insulating layer to form a lower sidewall pattern and a charge storage layer under each upper sidewall pattern, wherein the gate pattern and each upper sidewall pattern are used as an etching mask; and

forming a source region and a drain region in the semiconductor substrate.

9. The method as recited in claim 8 , further comprising doping impurities into an exposed portion of the semiconductor substrate in the gap region to form a channel region.

10. The method as recited in claim 8 , wherein forming the upper sidewall pattern on each exposed sidewall portion comprises:

forming an upper conductive layer on the semiconductor substrate; and

anisotropically etching the upper conductive layer to expose the lower conductive layer.

11. The method as recited in claim 8 , wherein the stacked insulating layer includes a tunnel oxide layer, a charge trapping layer and blocking insulating layer.

12. The method as recited in claim 8 , wherein the gate insulating layer is formed at a thickness having an equivalent oxide thickness less than an equivalent oxide thickness of the stacked insulating layer.