Method for removing metal foot during high-k dielectric/metal gate etching
View Patent ↗A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer ( 24 ) down to an underlying metal layer ( 22 ) to form an etched polysilicon structure ( 54 ) with polymer layers ( 50, 52 ) formed on its sidewall surfaces. The polymer layer ( 50, 52 ) are removed to expose an additional surface area ( 60, 62 ) of the metal layer ( 22 ), and dielectric layers ( 80, 82 ) are formed on the sidewall surfaces of the etched polysilicon structure ( 54 ). Next, the metal layer ( 22 ) is plasma etched to form an etched metal layer ( 95 ) with substantially vertical sidewall surfaces ( 97, 99 ) by simultaneously charging the dielectric layers ( 80, 82 ) to change plasma ion trajectories near the dielectric layers ( 80, 82 ) so that plasma ions ( 92, 94 ) impact the sidewall surfaces ( 97, 99 ) in a more perpendicular angle to enhance etching of the sidewall surfaces ( 97, 99 ) of the etched metal layer ( 95 ).
1. A method for forming a semiconductor structure, comprising:
forming a first metallic layer over a substrate;
depositing a polysilicon layer on the first metallic layer;
anisotropically etching the polysilicon layer down to the first metallic layer to form an etched polysilicon structure having a sidewall surface on which is formed a polymer layer;
removing the polymer layer from the sidewall surface of the etched polysilicon structure to expose an additional surface area of the first metallic layer; and
plasma etching the first metallic layer using the etched polysilicon structure for alignment to obtain an etched first metallic layer having a substantially vertical sidewall.
2. The method of claim 1 , further comprising forming a dielectric layer on the sidewall surface of the etched polysilicon structure after removing the polymer layer and before plasma etching the first metallic layer.
3. The method of claim 2 , where forming a dielectric layer comprises forming a fluorocarbon polymer film.
4. The method of claim 2 , where forming a dielectric layer comprises oxidizing the sidewall surface of the etched polysilicon structure using an oxygen plasma.
5. The method of claim 2 , where forming a dielectric layer comprises nitridating the sidewall surface of the etched polysilicon structure using a nitrogen plasma.
6. The method of claim 2 , where plasma etching comprises applying a plasma etch to the first metallic layer, thereby forming a sidewall surface of the first metallic layer while simultaneously charging the dielectric layer to change plasma ion trajectories near the dielectric layer so that plasma ions impact the sidewall surface of the first metallic layer to enhance etching of the sidewall surface of the first metallic layer.
7. The method of claim 1 , where the first metallic layer is formed from Ta x C y , Ta x N y , or TaSi x N y .
8. The method of claim 1 , where the first metallic layer is formed from Mo x N y or Ti x N y .
9. The method of claim 1 , where the first metallic layer is formed from W or W x N y .
10. The method of claim 1 , where removing the polymer layer comprises cleaning the polymer layer using a plasma etch or wet clean process.
11. A method for etching a metal gate electrode, comprising:
providing a substrate for forming a semiconductor device;
forming a first dielectric layer over the substrate;
forming a first metallic layer over the first dielectric layer;
forming a patterned polysilicon layer having a sidewall surface over the first metallic layer;
forming a sidewall dielectric layer on the sidewall surface of the patterned polysilicon layer; and
applying an angled etch process to etch the first metallic layer using the patterned polysilicon layer and sidewall dielectric layer for alignment to obtain an etched metal gate electrode having a substantially vertical sidewall.
12. The method of claim 11 , where the angled etch process comprises a plasma etch process which charges the sidewall dielectric layer.
13. The method of claim 11 , where the angled etch process stores charges in the sidewall dielectric layer to establish a localized electric field.
14. The method of claim 11 , where the angled etch process comprises a plasma etch process in which plasma ions have an ion impact trajectory that is substantially perpendicular to a corner surface of the first metallic layer being etched.
15. The method of claim 11 , where forming a patterned polysilicon layer comprises:
forming a polysilicon layer over the first metallic layer;
anisotropically etching the polysilicon layer down to the first metallic layer to leave a patterned polysilicon layer having a polymer layer formed on a sidewall surface; and
removing the polymer layer from the sidewall surface of the patterned polysilicon layer.
16. The method of claim 11 , where the sidewall dielectric layer comprises a fluorocarbon polymer.
17. The method of claim 11 , where the sidewall dielectric layer is formed by oxidizing or nitridating an exposed sidewall surface of the patterned polysilicon layer.
18. The method of claim 11 , where the angled etch process uses a plasma etch reactor with a high source power to charge the sidewall dielectric layer.
19. A method of forming metal gates in semiconductor device, comprising:
patterning and etching a polysilicon layer down to an underlying metallic layer to form an etched polysilicon structure having a sidewall surface on which is formed a polymer layer;
etching the polymer layer from the sidewall surface of the etched polysilicon structure to expose an additional surface area of the underlying metallic layer;
forming a thin nonconductive coating on the sidewall surface of the etched polysilicon structure; and
etching the underlying metallic layer with a charge prone plasma that charges the thin nonconductive coating to establish a localized electric field which directionalizes ions in the plasma to etch corner edges of the underlying metallic layer, thereby forming a metal gate having an etched metallic layer with vertical sidewalls.
20. The method of claim 19 , further comprising removing the thin conductive coating after etching the underlying metallic layer.