Test apparatus and test method

1. A test apparatus for testing switching speed of a combination circuit, where a level voltage based on a signal input from a first flip-flop (FF) is input to a second FF, comprising a pre-stage logic element outputting a first or second level voltage and a post-stage logic element to which the output signal of the pre-stage logic element is input, comprising:

a clock setting unit for setting a clock interval from the time when a clock signal is provided to the first FF to the time when a clock signal is provided to the second FF;

a threshold voltage setting unit for setting a threshold voltage of a post-stage field effect transistor (FET) to be different from that in a normal operation by setting a substrate voltage of the post-stage FET to have a value different from that in the normal operation of the circuit;

a first boundary value measuring unit for measuring a first boundary value of the substrate voltage for a normal operation of the circuit by changing the substrate voltage by said threshold voltage setting unit while the clock interval is set to the first clock interval; and

an error detecting unit for detecting an error in switching speed of the circuit based on the first boundary value,

wherein the post-stage logic element comprises the post-stage FET, a gate terminal of which the output signal is input to, for outputting a different level of voltage according to the case that the output signal voltage is higher or lower than a predetermined threshold voltage.

2. A test apparatus as claimed in claim 1 further comprising a second boundary value measuring unit for measuring a second boundary value of the substrate voltage for a normal operation of the circuit by changing the substrate voltage by said threshold voltage setting unit with the clock interval set to the second clock interval, wherein

said error detecting unit detects an error in switching speed of the circuit based on the first and second boundary values.

3. A test method for testing switching speed of a combination circuit, where a level voltage based on a signal input from a first flip-flop (FF) is input to a second FF, comprising a pre-stage logic element outputting a first or second level voltage and a post-stage logic element to which the output signal of the pre-stage logic element is input, wherein

said post-stage logic element comprises a post-stage field effect transistor (FET), the output signal being input to a gate terminal of said post-stage FET, for outputting a different level of voltage according to the case that the output signal voltage is higher or lower than a predetermined threshold voltage, the test method comprises:

a clock setting step of setting a clock interval from the time when a clock signal is provided to the first FF to the time when a clock signal is provided to the second FF;

a threshold voltage setting step of setting a threshold voltage of said post-stage FET to be different from that in a normal operation by setting a substrate voltage of the post-stage FET to have a value different from that in the normal operation of the circuit;

a first boundary value measuring step of measuring a first boundary value of the substrate voltage for a normal operation of the circuit by changing the substrate voltage in said threshold voltage setting step while the clock interval is set to the first clock interval; and

an error detecting step of detecting an error in switching speed of the circuit based on the first boundary value.