IP Library Granted Patent US 7,598,544
Granted Patent B2
US 7,598,544 · App. 11/332,080 · Granted Oct 6, 2009

Hybrid carbon nanotude FET(CNFET)-FET static RAM (SRAM) and method of making same

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Quick Facts
Patent No.
US 7,598,544
App. No.
11/332,080
Granted
Oct 6, 2009
Kind
B2
Abstract

Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.

Claims (8)

1. A static random access memory(SRAM), comprising:

two semiconductor-type field effect transistors (FETs), each FET having a semiconductor drain region and a semiconductor source region of a first type of semiconductor material, and each FET having a semiconductor channel region positioned between respective drain and source regions, said channel region made of a second type of semiconductor material, each FET further having a gate node in proximity to a respective channel region so as to be able to modulate the conductivity of the channel by electrically stimulating the gate, wherein the two semiconductor-type FETs are cross-coupled so that gate of one FET connects to the drain or source of the other; and

two nanotube FETs (NTFETs), each having a channel region made of non-woven nanotube fabric, connected to a respective source and drain region of a corresponding NTFET, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.

2. The SRAM cell of claim 1 , wherein the two semiconductor-type FETs are formed in a substrate, and the two NTFETs are positioned above the two semiconductor-type FETs.

3. The SRAM cell of claim 2 wherein the NTFETs are vertically aligned with a corresponding semiconductor-type FET.

4. The SRAM cell of claim 1 wherein the semiconductor-type FETs is an N-type FET and the channel of the NTFET is formed of p-type nanotubes.

5. The SRAM cell of claim 1 wherein the semiconductor-type FETs is an N-type FET and the channel of the NTFET is formed of ambipolar-type nanotubes.

6. The SRAM cell of claim 1 wherein NTFETs also include a back control gate.

Assignments (3)
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Nov 11, 2020
From: NANTERO, INC.
To: SILICON VALLEY BANK
Reel/Frame 054383/0632 →
LICENSE Recorded Aug 20, 2008
From: NANTERO, INC.
To: LOCKHEED MARTIN CORPORATION
Reel/Frame 021411/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2006
From: BERTIN, CLAUDE L.; MEINHOLD, MITCHELL; KONSEK, STEVEN L.; RUECKES, THOMAS; GUO, FRANK
To: NANTERO, INC.
Reel/Frame 017498/0115 →