Semiconductor device
View Patent ↗A fuse peripheral circuit shown in FIG. 2 has a fuse 10 , a potential difference imparting circuit 20 , a potential difference reducing circuit 30 , a terminal 40 , a memory circuit 50 , a transfer gate 60 , and a logic gate 70 . The potential difference imparting circuit 20 is configured as having a transfer gate 22 (first transfer gate), a terminal 24 (first terminal) and a terminal 26 , so as to give a predetermined potential difference between both ends of the fuse 10 when disconnection of the fuse 10 is judged. The potential difference reducing circuit 30 is configured as having a transfer gate 32 (second transfer gate), a terminal 34 (second terminal) and a terminal 36 , and reduces the potential difference between both ends of the fuse 10 applied by the above-described potential difference imparting circuit 20.
1. A semiconductor device comprising:
a fuse;
a potential difference imparting circuit imparting a predetermined potential difference between both ends of said fuse when disconnection of said fuse is judged; and
a potential difference reducing circuit reducing said potential difference applied between both ends of said fuse, said potential difference reducing circuit reducing a potential difference when disconnection of said fuse is not judged.
2. The semiconductor device as claimed in claim 1 , wherein said potential difference reducing circuit is configured so as to nearly equalize the potential on both sides of said fuse.
3. The semiconductor device as claimed in claim 1 , further comprising a terminal connected to one end of said fuse, supplying current to said fuse when said fuse is blown, said terminal being grounded.
4. The semiconductor device as claimed in claim 1 , wherein said potential difference imparting circuit comprises a first transfer gate, and a first terminal connected through said first transfer gate to the other end of said fuse, being applied with a second potential higher than a first potential applied to one end of said fuse; and
said potential difference reducing circuit comprises a second transfer gate, and a second terminal connected through said second transfer gate to the other end of said fuse, being applied with a third potential not lower than said first potential and lower than said second potential.
5. The semiconductor device as claimed in claim 1 , wherein said potential difference imparting circuit comprises a first transfer gate, and a first terminal connected through said first transfer gate to the other end of said fuse, being applied with a second potential lower than a first potential applied to one end of said fuse; and
said potential difference reducing circuit comprises a second transfer gate, and a second terminal connected through said second transfer gate to the other end of said fuse, being applied with a third potential higher than said second potential and not higher than said first potential.
6. The semiconductor device as claimed in claim 1 , further comprising a memory circuit storing a signal which indicates result of judgment on whether said fuse has been blown or not, and a third transfer gate provided on a path between said memory circuit and said fuse.
7. The semiconductor device as claimed in claim 6 , further comprising a logic gate which is provided on a path between said fuse and an input of said third transfer gate.