Enhanced MRAM reference bit programming structure
An MRAM circuit includes an MRAM array having a plurality of operational MRAM elements and a reference cell made up of one or more reference MRAM elements. A plurality of program lines within a first region are cladded with a flux-concentrating layer configured to focus a generated magnetic field while the portions of the program lines within a second region are uncladded so that the generated magnetic field is unfocused. Generally, the first region is associated with the operational MRAM elements and the second region is associated with the reference cell.
1. An MRAM circuit comprising:
a cladded region of a program line arranged near an operational MRAM element; and
an uncladded region of the program line arranged near a reference MRAM element.
2. The MRAM circuit of claim 1 , wherein cladded region includes a flux concentrating cladding to for focusing a generated magnetic field.
3. The MRAM circuit of claim 1 , wherein the operational MRAM element exhibits substantially the same physical properties as the reference MRAM element.
4. The MRAM circuit of claim 1 , wherein MRAM elements are MTJ's.
5. The MRAM circuit of claim 1 , wherein the MRAM elements are spin valves.
6. The MRAM circuit of claim 1 , wherein the reference MRAM element is physically separated from the operational MRAM element such that a magnetic field in the uncladded region sufficient to toggle the reference MRAM element would not toggle the operational MRAM element.
7. An MRAM circuit comprising:
an MRAM array including a plurality of operational MRAM elements;
a reference cell including one or more reference MRAM elements;
a plurality of program lines wherein each of the program lines includes a first region that is cladded and a second region that is uncladded, and wherein the first region is associated with the operational MRAM elements and the second region is associated with the reference cell.
8. The MRAM circuit of claim 7 wherein the first region includes a flux-concentrating layer configured to focus a generated magnetic field.
9. The MRAM circuit of claim 8 wherein the flux-concentrating layer includes a thin layer soft ferromagnetic material integrated into an inlaid copper interconnect.
10. The MRAM circuit of claim 7 , wherein the second region is separated from the first region such that a magnetic field generated within the second region would not normally toggle any of the operational MRAM elements.
11. The MRAM circuit of claim 7 , wherein a temperature sensitivity of the operational MRAM elements is substantially identical to a temperature sensitivity of the reference MRAM elements.
12. A memory device comprising:
a first magnetoresistive element configured for storing a datum;
a second magnetoresistive element configured for serving as a reference;
a program line disposed near the first magnetoresistive element and the second magnetoresistive element, wherein the program line includes a first cladded region configured to focus a generated magnetic field and a second uncladded region configured to create an unfocused generated magnetic field.
13. The memory device of claim 12 wherein the first magnetoresistive element is an MRAM element.
14. The memory device of claim 13 wherein the MRAM element includes two ferromagnetic layers separated by a dielectric layer.