Semiconductor device and manufacturing method thereof
A semiconductor device includes a semiconductor substrate, a monocrystalline channel region of a first conductivity type formed on the surface of the semiconductor substrate, a gate electrode formed on the channel region via a gate insulating film, a pair of source/drain electrodes of a second conductivity type provided on both sides of the gate electrode, metallic compound layers formed on the source/drain electrodes, stress application layers located under the respective source and drain electrodes and each having a crystal structure whose intrinsic lattice spacing is different from lattice spacing inherent in a substance constituting the source/drain electrodes, and first buried insulating regions disposed under the respective stress application layers.
1. A semiconductor device comprising:
a semiconductor substrate;
a monocrystalline channel region of a first conductivity type formed on the surface of the semiconductor substrate;
a gate electrode formed on the channel region via a gate insulating film;
a pair of source/drain electrodes of a second conductivity type provided on both sides of the gate electrode and having a monocrystalline or polycrystalline structure;
metallic compound layers formed on the source/drain electrodes;
first and second stress application layers placed in direct contact with bottom surfaces of the source/drain electrodes, respectively, and each having a crystal structure whose intrinsic lattice spacing is different from lattice spacing inherent in a substance constituting the source/drain electrodes;
first and second buried insulating regions placed in direct contact with bottom surfaces of the first and second stress application layers, respectively;
sealing insulating layers provided at both far-side and near-side ends of the first and second stress application layers, respectively, with respect to the gate electrode; and
liner insulating layers insoluble in an HF solution and formed between the stress application layers and the buried insulating regions.
2. The semiconductor device according to claim 1 , wherein the first and second buried insulating regions are in direct contact with the sealing insulating layers, respectively, and function as isolation insulating regions.
3. The semiconductor device according to claim 1 , wherein the metallic compound layers are located higher than a surface of the channel region.
4. The semiconductor device according to claim 1 , wherein each of the first and second stress application layers is a eutectic either of Si and Ge or of Si and C.
5. The semiconductor device according to claim 1 , wherein each of the first and second stress application layers includes a metal oxide.
6. The semiconductor device according to claim 1 , further comprising third buried insulating region formed under the channel region and between the stress application layers.
7. The semiconductor device according to claim 1 , wherein the metallic compound layers include NiSi.
8. The semiconductor device according to claim 1 , wherein the intrinsic lattice spacing of the stress application layers is larger than the lattice spacing of the source/drain electrodes when the second conductivity type of the source/drain electrodes is a p-type, while the intrinsic lattice spacing of the stress application layers is smaller than the lattice spacing of the source/drain electrodes when the second conductivity type of the source/drain electrodes is an n-type.
9. A semiconductor device comprising:
a semiconductor substrate;
a monocrystalline channel region of a first conductivity type formed on the surface of the semiconductor substrate;
a gate electrode formed on the channel region via a gate insulating film;
a pair of source/drain electrodes of a second conductivity type provided on both sides of the gate electrode and having a monocrystalline or polycrystalline structure;
metallic compound layers formed on the source/drain electrodes;
stress application layers placed in direct contact with bottom surfaces of the source/drain electrodes, respectively, and each having a crystal structure whose intrinsic lattice spacing is different from lattice spacing inherent in a substance constituting the source/drain electrodes;
buried insulating regions placed in direct contact with bottom surfaces of the stress application layers, respectively;
first sealing insulating layers provided at near-side ends of the stress application layers, respectively, with respect to the gate electrode; and
liner insulating layers insoluble in an HF solution and formed between the stress application layers and the buried insulating regions.
10. The semiconductor device according to claim 9 , further comprising second sealing insulating layers provided at far-side ends of the stress application layers, respectively, with respect to the gate electrode.
11. The semiconductor device according to claim 10 , wherein the buried insulating regions are in direct contact with the second sealing insulating layers, respectively, and function as isolation insulating regions.
12. The semiconductor device according to claim 9 , wherein the metallic compound layers are located higher than a surface of the channel region.
13. The semiconductor device according to claim 9 , wherein each of the stress application layers is a eutectic either of Si and Ge or of Si and C.
14. The semiconductor device according to claim 9 , wherein each of the stress application layers includes a metal oxide.