IP Library Granted Patent US 7,429,781
Granted Patent B2
US 7,429,781 · App. 11/339,866 · Granted Sep 30, 2008

Memory package

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Quick Facts
Patent No.
US 7,429,781
App. No.
11/339,866
Granted
Sep 30, 2008
Kind
B2
Abstract

A memory chip package with a controller die on a first side of a printed circuit board and a memory die on a second side of the same printed circuit board. The memory chip package is integrated into a microprocessor controlled device or alternatively is integrated into a portable memory card.

Claims (22)

1. A method of making a memory chip package, the method comprising:

providing a circuit board having first and second opposing faces;

attaching a FLASH EEPROM having memory cells to the first face of the circuit board;

attaching a controller die having a control logic to the second face of the circuit board, and

configuring the controller die to read and write data to the memory cells on the first face; and

providing data lines within the circuit board connecting the controller die to the EEPROM, the data lines operable to transfer data to and from the memory cells.

2. A method of making a microprocessor controlled device, the method comprising:

providing a memory chip package comprising a circuit board having a first and second face;

attaching a controller die to the first face of the circuit board;

attaching a memory die to the second face of the circuit board;

providing a system bus;

providing one or more input-output devices electrically coupled to the system bus and the memory chip package;

providing random access memory electrically coupled to the system bus and the memory chip package; and

providing a microprocessor.

3. A method of making a memory card, comprising:

attaching a plurality of memory die to the first face of a first circuit board;

attaching a plurality of controller die to the second face of the first circuit board, each controller die positioned beneath a memory die;

laminating the second face of the first circuit board to a first face of a second circuit board having a plurality of recesses such that the plurality of controller die fit within the plurality of recesses;

forming vias in the first and second circuit boards connecting the controller die beneath the memory die to the memory die to form a plurality of memory packages;

cutting the first and second circuit boards between the plurality of memory packages to form individual memory packages; and

placing an individual memory package into a memory card body such that a set of contacts on one of the first or second circuit boards is exposed from the body in order to make contact with a memory card receptacle.

4. The method of claim 3 , wherein the memory die is of a NAND flash architecture.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2021
From: SANDISK TECHNOLOGIES LLC
To: INNOVATIVE MEMORY SYSTEMS, INC.
Reel/Frame 058093/0991 →
CHANGE OF NAME Recorded May 25, 2016
From: SANDISK TECHNOLOGIES INC
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 038809/0472 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2011
From: SANDISK CORPORATION
To: SANDISK TECHNOLOGIES INC.
Reel/Frame 026318/0201 →