Semiconductor memory device and writing method thereof
View Patent ↗To provide a semiconductor memory device comprising a phase-change memory and having high compatibility with DRAM interface. The memory cell array 18 comprises a memory cell that includes a phase-change element provided at the intersection of a bit line and word line. A write address and data accompanying a write request are temporarily held in a write address register 15 and a data register 14 respectively, and a write operation is not performed on the memory cell array 18 in this cycle of write request. And when a next write request occurs, the held data is written to the memory cell array 18 . At this time, two write cycles—RESET cycle and SET cycle—are provided. Then the written contents of the memory cell and the rewrite data are compared, and after only SET cells are temporarily RESET (amorphization, increasing the resistance), it is operated so as to write only SET data (crystallization, lowering the resistance).
1. A write method of a semiconductor memory device for a memory cell, the write method comprising:
temporarily storing a write address and write data accompanying a write request in a write address register and a data register, respectively;
holding said write address and said write data in said write address register and said data register, respectively, until receipt of a next write request following said write request; and
writing said write data held in said data register to said memory cell according to said write address held in said write address register upon said receipt of said next write request,
wherein the memory cell comprises a programmable resistance element provided at the intersection of a bit line and a word line.
2. The write method of a semiconductor memory device as defined in claim 1 , wherein writing said write data in said data register to said memory cell comprises:
comparing the write address held in said address register with an address supplied by said next write request; and
performing a write control for the memory cell based on the result of the comparison.
3. The write method of a semiconductor memory device as defined in claim 2 , wherein performing said write control for the memory cell comprises:
reading a memory cell corresponding to said address supplied; and
comparing data written in said memory cell corresponding to said address supplied with said write data of said data register.
4. A read method of a semiconductor memory device wherein, when a read request occurs in the write method of a semiconductor memory device as defined in claim 1 , a read control is performed by comparing an address held in said write address register and an address corresponding to said read request.
5. The read method of a semiconductor memory device as defined in claim 4 wherein data held in said data register is read when an address held in said write address register and an address corresponding to said read request coincide.
6. The write method of a semiconductor memory device as defined in claim 1 , wherein said programmable resistance element is a programmable resistance memory element comprising a phase-change material.
7. A write method of a semiconductor memory device for a memory cell,
wherein a write address and write data accompanying a write request are temporarily stored in a write address register and a data register, respectively, and said write address and said write data are respectively held until a next write request,
wherein the memory cell comprises a programmable resistance element provided at the intersection of a bit line and a word line, and
wherein a write operation comprises a first write cycle where said resistance element is changed from a first state to a second state, and a second write cycle where said resistance element is changed from the second state to the first state.
8. The write method of a semiconductor memory device as defined in claim 7 wherein write control is performed so as to write only rewrite data corresponding to said first state after storing a write address and rewrite data in said write address register and said data register, respectively, comparing the written contents of a memory cell and said rewrite data, and temporarily turning only memory cells in the first state to the second state.
9. The write method of a semiconductor memory device as defined in claim 7 wherein said first write cycle is executed upon a first write request, a second write request following said first write request is detected, and said second write cycle is executed.
10. The write method of a semiconductor memory device as defined in claim 9 wherein newly supplied address and data are stored in said write address register and said data register, respectively, while said second write cycle is being executed.
11. The write method of a semiconductor memory device as defined in claim 7 wherein said resistance element has a resistance value in the first state higher than a resistance value of said resistance element in the second state.
12. The write method of a semiconductor memory device as defined in claim 7 wherein said resistance element has a resistance value in the first state lower than a resistance value of said resistance element in the second state.
13. The write method of a semiconductor memory device as defined in claim 7 , wherein said resistance element comprises a material that undergoes phase-change between said first and second states.
14. The write method of a semiconductor memory device as defined in claim 13 wherein said resistance element is programmed so that it is in a crystalline state when said phase-change material is in the first state and is in an amorphous state when said phase-change material is in the second state.
15. The write method of a semiconductor memory device as defined in claim 13 wherein said resistance element is programmed so that it is in an amorphous state when said phase-change material is in the first state and is in a crystalline state when said phase-change material is in the second state.
16. A semiconductor memory device comprising:
a memory cell array that comprises a memory cell including a programmable resistance element at an intersection of a bit line and a word line;
an address register that temporarily holds an address supplied externally;
a write address register that receives and holds said address held in said address register upon receipt of a write request; and
a data register that holds write data accompanying said write request; wherein
said write data held in said data register is written to said memory cell according to said address held in said write address register upon receipt of a next write request following said receipt of said write request.
17. The semiconductor memory device as defined in claim 16 , wherein said programmable resistance element is a programmable resistance memory element comprising a phase-change material.
18. A semiconductor memory device comprising:
a memory cell array that comprises a memory cell including a programmable resistance element at an intersection of a bit line and a word line;
an address register that temporarily holds an address supplied externally;
a write address register that receives and holds said address held in said address register upon a write request; and
a data register that holds write data accompanying said write request; wherein
said write data held in said data register is written to said memory cell according to said address held in said write address register corresponding to a next write request following said write request, and
the semiconductor memory device further comprises:
a read comparator that compares an address held in said address register and an address held in said write address register; and
a multiplexer circuit that selects between an output of said memory cell and an output of said data register based on a coincidence result outputted by said read comparator; wherein
an output of said data register becomes an output data that corresponds to a read request when an address held in said address register upon said read request and an address held in said write address register coincide.
19. A semiconductor memory device comprising:
a memory cell array that comprises a memory cell including a programmable resistance element at an intersection of a bit line and a word line;
an address register that temporarily holds an address supplied externally;
a write address register that receives and holds said address held in said address register upon a write request; and
a data register that holds write data accompanying said write request; wherein
said write data held in said data register is written to said memory cell according to said address held in said write address register corresponding to a next write request following said write request, and
the semiconductor memory device further comprises write control means for executing a first write cycle where said resistance element is changed from a first state to a second state and a second write cycle where said resistance element is changed from the second state to the first state.
20. The semiconductor memory device as defined in claim 19 wherein said write control means executes said first write cycle upon a first write request, detects a second write request following said first write request, and executes said second write cycle.
21. The semiconductor memory device as defined in claim 20 wherein newly supplied address and data are stored in said write address register and said data register, respectively, while said second write cycle is being executed.
22. The semiconductor memory device as defined in claim 19 wherein said resistance element has a resistance value in the first state higher than a resistance value of said resistance element in the second state.
23. The semiconductor memory device as defined in claim 19 wherein said resistance element has a resistance value in the first state lower than a resistance value of said resistance element in the second state.
24. The semiconductor memory device as defined in claim 19 , wherein said resistance element includes a material that undergoes phase-change between said first and second states.
25. The semiconductor memory device as defined in claim 24 wherein said resistance element is programmable so that it is in a crystalline state when said phase-change material is in the first state and is in an amorphous state when said phase-change material is in the second state.
26. The semiconductor memory device as defined in claim 24 wherein said resistance element is programmable so that it is in an amorphous state when said phase-change material is in the first state and is in a crystalline state when said phase-change material is in the second state.