Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate
A layer structure usable in manufacturing an integrated circuit is made, in a single apparatus, by a particular process in which a patterned substrate is provided. An electrolyte solution, out of which a conductive material can be plated under an applied potential, is supplied over a surface of the patterned substrate, and a potential is applied so as to deposit a film of the conductive material out of the electrolyte solution and over the surface of the patterned substrate. The film of conductive material is preferably polished as it is deposited. The conductive material is then removed from field regions of the patterned substrate, while deposits of the conductive material are left in features defined in the patterned substrate. The deposits of the conductive material are then electrically isolated, resulting in the layer structure.
1 . A process of making, in a single apparatus, a layer structure usable in manufacturing an integrated circuit comprising:
providing a patterned substrate,
supplying an electrolyte solution out of which a conductive material can be plated, under an applied potential, over a surface of said patterned substrate,
applying a potential so as to deposit a film of said conductive material out of the electrolyte solution and over said surface of said patterned substrate and polishing the film of said conductive material,
removing said conductive material from field regions of said patterned substrate while leaving deposits of said conductive material in features defined in said patterned substrate, and
electrically isolating said deposits of said conductive material.
2 . The process of claim 1 , wherein the field regions are regions of an insulator layer forming part of said patterned substrate.
3 . The process of claim 1 , and further comprising at least one additional operation of depositing conductive material after removing said conductive material and before electrically isolating said deposits.
4 . The process of claim 3 , and further comprising electro-etching said conductive material deposited by each additional operation of depositing.
5 . The process of claim 1 , wherein said potential is applied between said surface of said patterned substrate and an anode in the electrolyte solution.
6 . The process of claim 1 , wherein said patterned substrate includes an insulator layer and a barrier layer overlying said insulator layer, wherein said field regions are defined on said insulator layer, and wherein said deposits of said conductive material are electrically isolated by removing said barrier layer from said field regions.
7 . The process of claim 1 , and further comprising at least one additional operation of depositing conductive material before electrically isolating said deposits.
8 . The process of claim 7 , and further comprising annealing said deposits after said at least one additional operation of depositing conductive material.
9 . The process of claim 1 , and further comprising annealing said deposits after electrically isolating the deposits.
10 . The process of claim 1 , wherein electrically isolating said deposits is performed by chemical mechanical polishing.
11 . The process of claim 1 , wherein removing said conductive material is performed by electro-etching the film of the conductive material.
12 . The process of claim 11 , wherein the film is electroetched by inverting a polarity of said potential.
13 . The process of claim 1 , wherein electrically isolating said deposits is performed by reactive ion etching.
14 . The process of claim 1 , wherein electrically isolating said deposits is performed by wet etching.
15 . The process of claim 1 , wherein said conductive material is any of Cu, doped Cu, a copper allow, Pt, Ag, Au, Pd, Ni, a Pb—Sn allow, a lead-free solderable alloy, and a magnetic alloy.
16 . The process of claim 1 , wherein the film is deposited out of said electrolyte solution and polished simultaneously.
17 . A method of forming a planar conductive structure usable in manufacturing an interconnect for an integrated circuit, the method comprising:
providing a substrate having a top portion that includes a surface portion and a cavity portion, wherein the cavity portion has at least a first cavity having a width of less than one micron and a second cavity having a width larger than 10 microns; and
depositing a planar conductive layer within the cavity portion and on the surface portion, wherein the planar conductive layer, as deposited, has a predetermined thickness range over the surface portion that is between one tenth and one half of the thickness of the planar conductive layer within the cavity portion.
18 . The method of claim 17 , wherein providing comprises forming the top portion by depositing an insulator layer and a barrier layer overlying said insulator layer and forming the cavities in the insulator layer after depositing the insulator layer.
19 . The method of claim 17 , wherein the planar conductive material comprises copper or copper alloy.
20 . The method of claim 17 , wherein the planar conductive material comprises copper.
21 . The method of claim 17 , wherein depositing is electrochemical mechanical deposition, comprising:
feeding an electrolyte to the top portion, wherein the electrolyte is in contact with an anode; and
contacting a pad to the top portion while feeding the electrolyte while moving the substrate and pad with respect to each other.