Semiconductor memory device that requires refresh operations
View Patent ↗A semiconductor memory device includes a refresh counter that outputs an address of a word line to be refreshed, a ROM circuit that stores a relevant address related to a refresh defective address, and a multiple refresh control circuit that simultaneously or continuously activates the refresh defective address and the relevant address within one refresh cycle in response to a fact that the ROM circuit detects the relevant address. The multiple refresh control circuit excludes a pattern having a risk that a power supply potential or a ground potential varies greatly such as a pattern that the multiple refresh occurs continuously. With this arrangement, a refresh defective cell can be saved while restricting the variation in the power supply potential or the ground potential.
1. A semiconductor memory device, comprising:
a plurality of word lines including a first word line and a second word line;
a plurality of memory cells connected to the word lines;
a first unit that outputs an address of a word line to be activated;
a second unit that carries out multiple refresh of simultaneously or continuously activating the first word line corresponding to the defective memory cell and the second word line related to the first word line, within one refresh cycle, in response to a fact that at least the first unit outputs an address of the second word line; and
a third unit that limits an appearance pattern of the multiple refresh.
2. The semiconductor memory device as claimed in claim 1 , wherein said first unit includes a refresh counter that performs increment operation or decrement operation in response to a refresh command supplied from the outside.
3. The semiconductor memory device as claimed in claim 1 , wherein said second unit also carries out the multiple refresh in response to a fact that the first unit outputs an address of the first word line.
4. The semiconductor memory device as claimed in claim 2 , wherein said second unit also carries out the multiple refresh in response to a fact that the first unit outputs an address of the first word line.
5. The semiconductor memory device as claimed in claim 1 , wherein said second unit includes a ROM circuit that stores at least a part of bits of the address of the first word line.
6. The semiconductor memory device as claimed in claim 5 , wherein said ROM circuit stores only a part of bits including at least a lowest bit of the address output by the first unit.
7. The semiconductor memory device as claimed in claim 1 , wherein said third unit prohibits the multiple refresh in a next refresh cycle, when the appearance pattern of the multiple refresh coincides with a predetermined multiple refresh prohibited pattern.
8. The semiconductor memory device as claimed in claim 7 , wherein said third unit permits the multiple refresh in the next refresh cycle, when the multiple refresh is not carried out during a predetermined period or at a predetermined number of cycles.
9. The semiconductor memory device as claimed in claim 7 , wherein said third unit permits the multiple refresh in the next refresh cycle, when a read operation or a write operation is carried out.
10. The semiconductor memory device as claimed in claim 8 , wherein said third unit permits the multiple refresh in the next refresh cycle, when a read operation or a write operation is carried out.
11. A semiconductor memory device, comprising:
a plurality of word lines;
a plurality of memory cells connected to the word lines; and
a refresh circuit that refreshes the plurality of memory cells by sequentially activating the plurality of word lines,
in a normal state, said refresh circuit refreshing a first address and a second address corresponding to the first address in the same refresh cycle, in response to a fact that a refresh operation of the first address is instructed,
in a prohibited state, said refresh circuit refreshing the first address and the second address in separate refresh cycles, in response to a fact that the refresh operation of the first address is instructed.
12. The semiconductor memory device as claimed in claim 11 , wherein when an appearance pattern of a multiple refresh for refreshing the first and the second addresses in the same refresh cycle coincides with a multiple refresh prohibited pattern, a state of the semiconductor memory device is transited from the normal state to the prohibited state.
13. The semiconductor memory device as claimed in claim 12 , wherein when the multiple refresh is not carried out during a predetermined period or at a predetermined number of cycles, a state of the semiconductor memory device is transited from the prohibited state to the normal state.
14. The semiconductor memory device as claimed in claim 12 , wherein when a read operation or a write operation is carried out, a state of the semiconductor memory device is transited from the prohibited state to the normal state.
15. The semiconductor memory device as claimed in claim 13 , wherein when a read operation or a write operation is carried out, a state of the semiconductor memory device is transited from the prohibited state to the normal state.
16. A semiconductor memory device, comprising:
a refresh counter of which count is incremented or decremented in response to a refresh signal;
a ROM circuit group that detects a coincidence of a count value of the refresh counter and a plurality of stored addresses; and
a means for prohibiting the refresh counter to be incremented or decremented, in response to a fact that a coincidence pattern detected by the ROM circuit group corresponds to a predetermined pattern.
17. The semiconductor memory device as claimed in claim 16 , wherein said prohibiting means inverts a part of bits of the count value of the refresh counter, in response to a fact that the coincidence pattern detected by the ROM circuit group corresponds to said predetermined pattern.