Memory controller operating in a system with a variable system clock
View Patent ↗The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.
1. A method for transferring read data from memory driven by a constant memory clock to a processor driven by a variable processor clock by means of an asynchronous read buffer configured to receive read data from memory driven by the memory clock and send read data to the processor driven by the processor clock, comprising:
receiving a slow mode request from a clock controller to lower a frequency of the processor clock;
in response to receiving the slow mode request, stalling processing of read commands until all pending read commands are completed;
determining a rate for issuing read commands; and
after the pending read commands are completed, issuing read commands at the determined rate, wherein the determined rate is selected to prevent overflow of the read buffer.
2. The method of claim 1 , further comprising, sending an acknowledge signal to the clock controller after the pending read commands are completed to change the frequency of the processor clock.
3. The method of claim 1 , wherein determining the rate comprises selecting a rate that reduces power dissipation and enhances performance.
4. The method of claim 1 , comprising issuing read commands at the determined rate by waiting for a predetermined number of clock cycles before issuing the read command.
5. The method of claim 4 , wherein the predetermined number of clock cycles are based on a ratio between the frequency of the processor clock and a frequency of the memory clock.
6. The method of claim 4 , wherein the predetermined number of clock cycles depend on a value contained in a command pacing register.
7. A method for transferring write data from a processor driven by a variable processor clock to memory driven by a constant memory clock by means of an asynchronous write buffer configured to receive write data from the processor driven by the processor clock and send write data to the memory driven by the memory clock, comprising:
receiving a slow mode request from a clock controller to lower a frequency of the processor clock;
in response to receiving the slow mode request, transferring pending write commands and writing data to memory; and
after transferring the pending write commands and write data to memory, receiving subsequent write commands and write data, and writing the subsequent write data to memory only if the subsequent write data is available in the asynchronous write buffer.
8. The method of claim 7 , wherein determining whether subsequent write data is available in the asynchronous write buffer comprises determining whether a moved signal is asserted, wherein the moved signal indicates that the subsequent write data has been transferred to the asynchronous write buffer driven by the processor clock.
9. The method of claim 8 , wherein transferring subsequent write data from the write buffer to memory driven by the memory clock in response to receiving a launch signal, wherein the launch signal is asserted if the moved signal is asserted.