IP Library Granted Patent US 7,357,878
Granted Patent B2
US 7,357,878 · App. 11/351,015 · Granted Apr 15, 2008

Etchant, and method for fabricating a thin film transistor subtrate including conductive wires using the etchant and the resulting structure

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Quick Facts
Patent No.
US 7,357,878
App. No.
11/351,015
Granted
Apr 15, 2008
Kind
B2
Abstract

Provided are an etchant, a method for fabricating a wire using the etchant, and a method for fabricating a thin film transistor (TFT) substrate using the etchant. The etchant includes a material having the formula 1, ammonium acetic acid, and the remainder of deionized water, wherein the formula 1 is expressed by: M(OH) X L Y   (1) where M indicates Zn, Sn, Cr, Al, Ba, Fe, Ti, Si, or B, X indicates 2 or 3, L indicates H 2 O, NH 3 , CN, COR, or NH 2 R, Y indicates 0, 1, 2, or 3, and R indicates an alkyl group.

Claims (32)

1. A method for fabricating a wire, the method comprising:

forming multiple-layers including conductive oxide layers and an Ag conductive layer formed of Ag or an Ag-alloy on a substrate; and

etching the multiple-layers using an etchant including a material having the formula 1, ammonium acetic acid, and the remainder of deionized water, wherein the formula 1 is expressed by:

M(OH) x L y   (1)

where M indicates Zn, Sn, Cr, Al, Ba, Fe, Ti, Si, or B, X indicates 2 or 3, L indicates H 2 O, NH 3 , CN, COR, or NH 2 R, Y indicates 0, 1, 2, or 3, and R indicates an alkyl group.

2. The method of claim 1 , wherein the forming of the multiple-layers comprises sequentially depositing a first conductive oxide layer, the conductive layer formed of Ag or the Ag-alloy, and a second conductive oxide layer on the substrate.

3. The method of claim 1 , wherein the amount of the material of formula 1is in a range of 0.1-5 wt % and ammonium acetic acid is in a range 0.001-0.1 wt %.

4. The method of claim 1 or 3 , further comprising phosphoric acid in a range of 60-70 wt %, nitric acid in a range of 0.5-5 wt %, and acetic acid in a range of 2-10 wt %.

5. The method of claim 1 , wherein the substrate is formed of an insulator or a semiconductor.

6. The method of claim 1 , wherein the etching is performed at a temperature of 30-50° C.

7. The method of claim 1 , wherein the etching is performed using spraying.

8. The method of claim 1 , wherein the etching is performed for 30-100 seconds.

9. The method of claim 1 , wherein the etching is performed on the respective layers forming the multiple-layers in a batch manner.

10. The method of claim 1 , wherein the conductive oxide layers are formed of indium tin oxide (ITO) or indium zinc oxide (IZO).

11. A method for fabricating a thin film transistor (TFT) substrate, the method comprising:

forming gate multiple-layers to be formed into a gate including conductive oxide layers and a conductive layer formed of Ag or an Ag-alloy on a substrate;

forming a gate wire by patterning the gate multiple-layers;

forming a gate insulating layer and a semiconductor layer on the substrate and the gate wire;

forming data multiple-layers including conductive oxide layers and a conductive layer formed of Ag or an Ag-alloy on the semiconductor layer; and

forming a data wire by patterning the data multiple-layers;

wherein the forming of the gate wire and/or the data wire comprises etching using an etchant including a material having the formula 1, ammonium acetic acid, and the remainder of deionized water, wherein the formula 1 is expressed by:

M(OH) x L y   (1)

where M indicates Zn, Sn, Cr, Al, Ba, Fe, Ti, Si, or B, X indicates 2 or 3, L indicates H 2 O, NH 3 , CN, COR, or NH 2 R, Y indicates 0, 1, 2, or 3, and R indicates an alkyl group.

12. The method of claim 11 , wherein the forming of the gate multiple-layers comprises sequentially depositing a first conductive oxide layer, the conductive layer formed of Ag or the Ag-alloy, and a second conductive oxide layer on the substrate.

13. The method of claim 11 , wherein the forming of the data multiple-layers comprises sequentially depositing a first conductive oxide layer, the conductive layer formed of Ag or the Ag-alloy, and a second conductive oxide layer on the semiconductor layer.

14. The method of claim 11 , wherein an amount of the material of formula 1 is in a range of 0.1-5 wt % and ammonium acetic acid is in a range 0.001-0.1 wt %.

15. The method of claim 11 or 14 , further comprising phosphoric acid in a range of 60-70 wt %, nitric acid in a range of 0.5-5 wt %, and acetic acid in a range of 2-10 wt %.

16. The method of claim 11 , wherein the etching is performed at a temperature of 30-50° C.

17. The method of claim 11 , wherein the etching is performed using spraying.

18. The method of claim 11 , wherein the etching is performed for 30-100 seconds.

19. The method of claim 11 , wherein the etching is performed on the respective layers forming the gate multiple-layers and the data multiple-layers in a batch manner.

20. The method of claim 11 , wherein the conductive oxide layers of the data multiple-layers and the gate multiple-layers are formed of indium tin oxide (ITO) or indium zinc oxide (IZO).

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 029008/0339 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2007
From: PARK, HONG-SICK; KIM, SHI-YUL; CHOUNG, JONG-HYUN; SHIN, WON-SUK
To: SAMSUNG ELECTRONICS CO., LTD
Reel/Frame 019515/0222 →