Power conservation via DRAM access reduction
View Patent ↗Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein. In one usage scenario, data retained in the buffer/mini-cache is graphics refresh data maintained in a compressed format.
1. A memory element including:
a memory array; and
a controller coupled to the memory array;
wherein in response to a buffer-activation event, the controller directs the memory array to operate as a buffer responsive to a portion of a plurality of device accesses by a device and wherein in response to a cache-activation event, the controller directs the memory array to operate as a cache responsive to processor accesses by a processor;
wherein the device is a graphics display processor and the device accesses include at least one non-cacheable read access and at least one non-cacheable write access.
2. The memory element of claim 1 , wherein the controller is further configured, to flush the memory array upon detecting any of the events.
3. The memory element of claim 1 , wherein the buffer-activation event includes at least one of:
the instruction processor switching to a lower power state,
the instruction processor switching to a lower performance state, and
the instruction processor turning off snooping; wherein the cache-activation event includes at least one of:
the instruction processor switching to a higher power state,
the instruction processor switching to a higher performance state, and
the instruction processor turning on snooping.
4. The memory element of claim 1 , wherein the portion of the device accesses is determined in part by examination of a physical address associated with each respective one of the device accesses.
5. The memory element of claim 1 , wherein the instruction processor is enabled to execute variable-length instructions and the processor accesses include at least one cacheable processor read access and at least one cacheable processor write access.
6. A system including:
a storage array operable according to a cacheable-access mode responsive to cacheable accesses from an instruction processor and a non-cacheable-access mode responsive to a portion of a plurality of non-cacheable, buffered accesses from a device; and
a storage controller;
wherein the storage controller is enabled to recognize a cacheable-access-transition event and in response thereto to transition the storage array from the non-cacheable-access mode to the cacheable-access mode,
wherein the cacheable-access-transition event includes at least one of:
the instruction processor switching to a higher power state,
the instruction processor switching to a higher performance state, and
the instruction processor turning on snooping;
wherein the non-cacheable-access-transition event includes at least one of:
the instruction processor switching to a lower power state;
the instruction processor switching to a lower performance state, and
the instruction processor turning off snooping; and
wherein the portion of the non-cacheable accesses is determined based at least in part on respective physical addresses associated with each of the non-cacheable accesses.
7. The system of claim 6 , wherein the storage controller is further enabled to recognize a non-cacheable-access-transition event and in response thereto to transition the storage array from the cacheable-access mode to the non-cacheable-access mode.
8. The system of claim 6 , wherein the storage controller is further enabled to direct a flush of the storage array during the transition from the cacheable-access mode to the non-cacheable-access mode.
9. The system of claim 6 , wherein the storage controller is further enabled to direct a flush of the storage array during the transition from the non-cacheable-access mode to the cacheable-access mode.
10. The system of claim 6 , further including the instruction processor.
11. The system of claim 6 , further including the device.
12. The system of claim 11 , wherein the device is a graphics display processor.
13. The system of claim 12 , wherein the graphics display processor is enabled to generate some of the non-cacheable accesses.
14. The system of claim 12 , wherein the graphics display processor is enabled to generate at least one of the non-cacheable accesses, and the at least one of the non-cacheable accesses is satisfied by data from the storage array.
15. The system of claim 12 , wherein the graphics display processor is enabled to generate at least one of the non-cacheable accesses, and the at least one of the non-cacheable accesses is allocated to one of a plurality of lines implemented by the storage array.
16. The system of claim 12 , further including a Dynamic Random Access Memory (DRAM) controller coupled to a DRAM and response to at least one of the non-cacheable accesses that is distinct from the portion of the non-cacheable accesses.
17. The system of claim 6 , wherein the storage array is implemented in an outer-level cache associated with the instruction processor.
18. The system of claim 6 , wherein a portion of the storage array is operable according to the non-cacheable-access mode, and the portion is determined in part based on an allocation of one or more ways of the outer-level cache.
19. A method, comprising:
detecting, while operating a storage structure according to a non-cacheable mode, a transition-to-cacheable-mode event;
flushing, in response to the detecting of the transition-to-cacheable-mode event, the storage structure, while operating the storage structure according to a cacheable mode, detecting a transition-to-non-cacheable-mode event; and
flushing, in response to the detecting of the transition-to-non-cacheable-mode event, the storage structure;
searching, while operating the storage structure according to the non-cacheable mode, the storage structure for data responsive to a non-cacheable access from a device, the non-cacheable access having a physical address between a strating physical address and an ending physical address; and
responding, while operating the storage structure according to the cacheable mode, to cacheable accesses from an instruction processor.
20. The method of claim 19 , wherein the transition-to-cacheable-mode event includes at least one of:
the instruction processor switching to a higher power state;
the instruction processor switching to a higher performance state; or
the instruction processor turning on snooping; and
wherein the transition-to-non-cacheable-mode event includes at least one of:
the instruction processor switching to a lower power state,
the instruction processor switching to a lower performance state; or
the instruction processor turning off snooping.
21. The method of claim 19 , further including marking lines of the storage structure allocated during operation in the cacheable mode as distinct from lines of the storage structure allocated during operation in the non-cacheable mode.
22. The method of claim 21 , wherein the flushing is dependent upon the marking of the lines of storage.
23. The method of claim 19 , wherein the device is a graphics display processor.
24. The method of claim 23 , further including the graphics display processor storing compressed data in the storage structure.
25. The method of claim 24 , further including the instruction processor receiving an uncompressed representation of at least a portion of the compressed data.