IP Library Assignment 020957/0434
Patent Assignment
Reel/Frame 020957/0434

Assignment of Assignor's Interest

Recorded: 2008-05-16 Pages: 8
Assignor
MONTALVO SYSTEMS, INC.
Executed: 2008-04-17
Assignee
SUN MICROSYSTEMS, INC.
4150 NETWORK CIRCLE, SANTA CLARA, CALIFORNIA, 95054
Covered Properties (56)
Small and Power-Efficient Cache That Can Provide Data for Background Dma Devices While the Processor Is in a Low-Power State
Patent: 7,412,570 →
Application: 11/351,058 →
Publication: US 2007/0130382
Power Conservation via Dram Access Reduction
Patent: 7,516,274 →
Application: 11/351,070 →
Publication: US 2007/0113015
Reducing Power Consumption for Processing of Common Values in Microprocessor Registers and Execution Units
Patent: 7,631,207 →
Application: 11/408,784 →
System and Method for Optimizing a Memory Controller
Patent: 7,627,730 →
Application: 11/416,872 →
System and Method for Conserving Power
Patent: 7,797,563 →
Application: 11/450,103 →
Cache Operations with Hierarchy Control
Patent: 7,539,819 →
Application: 11/543,598 →
Dynamic Resource Allocation Among Master Processors That Require Service from a Coprocessor
Patent: 7,490,223 →
Application: 11/555,253 →
Publication: US 2007/0198983
Synchronizing Master Processor by Stalling When Tracking of Coprocessor Rename Register Resource Usage Count for Sent Instructions Reaches Credited Apportioned Number
Patent: 7,490,225 →
Application: 11/555,258 →
Publication: US 2007/0198984
Coprocessor Receiving Renamed Register Identifier from Master to Complete an Operation Upon Register Data Ready
Patent: 7,493,471 →
Application: 11/555,263 →
Publication: US 2007/0198813
Small and Power-Efficient Cache That Can Provide Data for Background Dma Devices While the Processor Is in a Low-Power State
Patent: 7,958,312 →
Application: 11/559,069 →
Publication: US 2007/0186057
Power Conservation via Dram Access Reduction
Patent: 7,904,659 →
Application: 11/559,133 →
Publication: US 2007/0214323
Power Conservation via Dram Access
Patent: 7,899,990 →
Application: 11/559,192 →
Publication: US 2009/0132764
Maintaining Memory Coherency with a Trace Cache
Patent: 7,747,822 →
Application: 11/591,024 →
Prediction of Data Values Read from Memory by a Microprocessor Using the Storage Destination of a Load Operation
Patent: 7,788,473 →
Application: 11/646,008 →
Nand/Nor Registers
Patent: 7,834,663 →
Application: 11/737,103 →
Publication: US 2008/0258775
Dynamic Dual Output Latch
Patent: 7,710,155 →
Application: 11/738,287 →
Publication: US 2008/0258788
Enhanced Signaling Sensitivity Using Multiple References
Patent: 7,957,472 →
Application: 11/745,370 →
Publication: US 2008/0279310
Symmetrical Differential Amplifier
Patent: 7,567,124 →
Application: 11/764,159 →
Publication: US 2008/0309408
Memory Cells with Power Switch Circuit for Improved Low Voltage Operation
Patent: 7,570,537 →
Application: 11/777,074 →
Publication: US 2009/0016138
Virtual Core Management
Patent: 7,802,073 →
Application: 11/781,726 →
Trace Unit with a Decoder, A Basic-Block Builder, and a Multi-Block Builder
Application: 11/781,937 →
Method and System for Promoting Traces in an Instruction Processing Circuit
Application: 11/781,949 →
System and Method for Ensuring Coherency in Trace Execution
Patent: 8,032,710 →
Application: 11/782,163 →
Method and System for Utilizing a Common Structure for Trace Verification and Maintaining Coherency in an Instruction Processing Circuit
Patent: 8,015,359 →
Application: 11/782,238 →
Concurrent Vs. Low Power Branch Prediction
Patent: 7,966,479 →
Application: 11/880,859 →
Trace Unit with a Trace Builder
Patent: 7,949,854 →
Application: 11/880,861 →
Trace Unit with a Decoder, a Basic-Block Cache, a Multi-Block Cache, and Sequencer
Patent: 7,987,342 →
Application: 11/880,862 →
Trace Unit with an Op Path from a Decoder (Bypass Mode) and from a Basic-Block Builder
Patent: 7,953,961 →
Application: 11/880,863 →
Instruction Cache, Decoder Circuit, Basic Block Cache Circuit and Multi-Block Cache Circuit
Patent: 7,953,933 →
Application: 11/880,875 →
Trace Unit
Patent: 8,037,285 →
Application: 11/880,882 →
Graceful Degradation in a Trace-Based Processor
Patent: 7,783,863 →
Application: 11/923,638 →
Abort Prioritization in a Trace-Based Processor
Patent: 7,870,369 →
Application: 11/923,640 →
Dynamic Voltage Scaling for Self-Timed or Racing Paths
Patent: 7,622,979 →
Application: 11/932,311 →
Publication: US 2009/0108899
Memory Device with Split Power Switch
Patent: 7,952,910 →
Application: 11/932,555 →
Publication: US 2008/0273412
Method of Selectively Powering Memory Device
Application: 11/932,643 →
Publication: US 2008/0266995
Method of Operating Memory Cell Providing Internal Power Switching
Patent: 7,626,853 →
Application: 11/932,738 →
Elastic Power for Read and Write Margins
Patent: 7,672,187 →
Application: 11/932,967 →
Publication: US 2008/0186791
Virtual Core Management
Patent: 8,219,788 →
Application: 11/933,267 →
Virtual Core Management
Patent: 7,797,512 →
Application: 11/933,297 →
Virtual Core Management
Patent: 8,225,315 →
Application: 11/933,319 →
Virtual Core Management
Patent: 8,543,843 →
Application: 11/933,349 →
Elastic Power for Read Margin
Patent: 7,869,263 →
Application: 11/938,196 →
Publication: US 2008/0186795
Promoting and Appending Traces in an Instruction Processing Circuit Based Upon a Bias Value
Patent: 7,814,298 →
Application: 11/941,883 →
Flag Optimization of a Trace
Patent: 7,849,292 →
Application: 11/941,900 →
Emit Vector Optimization of a Trace
Patent: 7,937,564 →
Application: 11/941,908 →
Symbolic Renaming Optimization of a Trace
Patent: 8,499,293 →
Application: 11/941,912 →
Microprocessor Including a Display Interface in the Microprocessor
Patent: 9,336,752 →
Application: 11/963,579 →
Microprocessor Including a Display Interface in the Microprocessor
Patent: 8,890,876 →
Application: 11/963,603 →
Trace Based Deallocation of Entries in a Versioning Cache Circuit
Patent: 8,051,247 →
Application: 12/030,846 →
Memory Ordering Queue/Versioning Cache Circuit
Patent: 8,024,522 →
Application: 12/030,851 →
Trace Based Rollback of a Speculatively Updated Cache
Patent: 7,877,630 →
Application: 12/030,852 →
Data Cache Rollbacks for Failed Speculative Traces with Memory Operations
Patent: 8,370,609 →
Application: 12/030,854 →
Memory Ordering Queue Tightly Coupled with a Versioning Cache Circuit
Patent: 7,779,307 →
Application: 12/030,857 →
Cache Rollback Acceleration via a Bank Based Versioning Cache Circuit
Patent: 8,370,576 →
Application: 12/030,858 →
Rolling Back a Speculative Update of a Non-Modifiable Cache Line
Patent: 8,010,745 →
Application: 12/030,859 →
Checking for a Memory Ordering Violation After a Speculative Cache Write
Patent: 8,019,944 →
Application: 12/030,862 →
Related Assignments (21)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Apr 21, 2006
From: SONG, SEUNGYOON PETER; HARTMAN, JOREL
To: MONTALVO SYSTEMS, INC.
Reel/Frame 017801/0323 →
Assignment of Assignor's Interest Apr 24, 2006
From: MOLL, LAURENT R.; CHENG, YU QING; GLASKOWSKY, PETER N.; SONG, SEUNGYOON PETER
To: MONTALVO SYSTEMS
Reel/Frame 017518/0156 →
Assignment of Assignor's Interest Apr 24, 2006
From: MOLL, LAURENT R.; SONG, SEUNGYOON PETER; GLASKOWSKY, PETER N.; CHENG, YU QING
To: MONTALVO SYSTEMS
Reel/Frame 017518/0150 →
Assignment of Assignor's Interest May 2, 2006
From: MOLL, LAURENT
To: MONTALVO SYSTEMS, INC.
Reel/Frame 017865/0651 →
Assignment of Assignor's Interest Jun 9, 2006
From: MOLL, LAURENT R.; ROWLANDS, JOSEPH
To: MONTALVO SYSTEMS, INC.
Reel/Frame 017988/0735 →
Assignment of Assignor's Interest Oct 17, 2006
From: MOLL, LAURENT R.
To: MONTALVO SYSTEMS, INC.
Reel/Frame 018401/0336 →
Assignment of Assignor's Interest Oct 31, 2006
From: FAVOR, JOHN G.; THAIK, RICHARD W.
To: MONTALVO SYSTEMS, INC.
Reel/Frame 018488/0272 →
Assignment of Assignor's Interest Dec 26, 2006
From: NELSON, CHRIS; ASHCRAFT, MATTHEW; FAVOR, JOHN GREGORY; SONG, SEUNGYOON PETER
To: MONTALVO SYSTEMS, INC.
Reel/Frame 018742/0768 →
Assignment of Assignor's Interest Apr 18, 2007
From: WENDELL, DENNIS
To: MONTALVO SYSTEMS, INC.
Reel/Frame 019178/0867 →
Assignment of Assignor's Interest May 2, 2007
From: FAVOR, JOHN GREGORY; NELSON, CHRISTOPHER P.
To: MONTALVO SYSTEMS, INC.
Reel/Frame 019240/0075 →
Assignment of Assignor's Interest May 2, 2007
From: FAVOR, JOHN GREGORY; NELSON, CHRISTOPHER P.
To: MONTALVO SYSTEMS, INC.
Reel/Frame 019240/0048 →
Assignment of Assignor's Interest May 2, 2007
From: FAVOR, JOHN GREGORY; NELSON, CHRISTOPHER P.
To: MONTALVO SYSTEMS, INC.
Reel/Frame 019240/0051 →
Assignment of Assignor's Interest May 22, 2007
From: WU, HUNG JEN (HENRY); LIH, YOLIN
To: MONTALVO SYSTEMS, INC.
Reel/Frame 019328/0972 →
Assignment of Assignor's Interest May 30, 2007
From: MOLL, LAURENT R.; SONG, SEUNGYOON P.; GLASKOWSKY, PETER N.; CHENG, YU Q.
To: MONTALVO SYSTEMS, INC.
Reel/Frame 019354/0994 →
Assignment of Assignor's Interest May 30, 2007
From: MOLL, LAURENT R.; SONG, SEUNGYOON P.; GLASKOWSKY, PETER N.; CHENG, YU Q.
To: MONTALVO SYSTEMS, INC.
Reel/Frame 019355/0223 →
Assignment of Assignor's Interest May 30, 2007
From: MOLL, LAURENT R.; GLASKOWSKY, PETER N.; CHENG, YU Q.; SONG, SEUNGYOON P.
To: MONTALVO SYSTEMS, INC.
Reel/Frame 019354/0871 →
Assignment of Assignor's Interest Jul 9, 2007
From: LIH, YOLIN
To: MONTALVO SYSTEMS, INC.
Reel/Frame 019532/0970 →
Assignment of Assignor's Interest Jul 12, 2007
From: BHATIA, AJAY
To: MONTALVO SYSTEMS, INC.
Reel/Frame 019551/0788 →
Assignment of Assignor's Interest Jun 30, 2008
From: MONTALVO SYSTEMS, INC.
To: SUN MICROSYSTEMS, INC.; SUN MICROSYSTEMS TECHNOLOGY LTD
Reel/Frame 021171/0578 →
Assignment of Assignor's Interest Jul 7, 2008
From: MONTALVO SYSTEMS, INC.
To: SUN MICROSYSTEMS, INC.; SUN MICROSYSTEMS TECHNOLOGY LTD.
Reel/Frame 021198/0009 →
Corrective Assignment to Correct the Assignee Previously Recorded on Reel 020957 Frame 0434. Assignor(S) Hereby Confirms the Correct Assignees Are Sun Microsystems, Inc. and Sun Microsystems Technology Ltd. Aug 23, 2011
From: MONTALVO SYSTEMS, INC.
To: SUN MICROSYSTEMS, INC.; SUN MICROSYSTEMS TECHNOLOGY LTD.
Reel/Frame 026794/0962 →