Enhanced signaling sensitivity using multiple references
View Patent ↗A receiver circuit uses two or more comparators to detect the received data signal. Each comparator is set to compare the data signal to a different reference signal. The output signals of the comparators are received into a detector circuit, which provides a third output signal that establishes the logic state of the received signal based on whether or not the output signals of the comparators are equal. Depending on the logic state of the data signal, one of the comparators provides its output signal sooner than the other. Each comparator may be implemented by a differential amplifier. In one embodiment, the reference signals are threshold voltages which may be provided by the tripping voltages at the trip points for the logic HIGH and LOW states.
1. A receiver circuit for receiving a data signal, comprising:
a first comparator receiving the data signal and a first reference voltage to provide a first output signal representing a first detected logic state of the data signal;
a second comparator receiving the data signal and a second reference voltage to provide a second output signal representing a second detected logic state of the data signal; and
a detector circuit receiving the first and second output signals and providing a third output signal, the third output signal changes state when the first and the second detected logic states agree, wherein
the first comparator provides the first output signal sooner than the second comparator provides the second output signal when the data signal transitions to a first logic state, and
the second comparator provides the second output signal sooner than the first comparator provides the first output signal when the data signal transitions to a second logic state opposite the first logic state.
2. A receiver as in claim 1 , further comprising a second detector circuit receiving the first, second and third output signals, the second detector configured to provide a fourth output signal representing the earlier of the first and the second logic signals in response to the data signal transition.
3. A receiver circuit as in claim 2 , wherein the second detector circuit comprises a multiplexer.
4. A receiver circuit as in claim 3 , further comprising a latched stage receiving the fourth output signal.
5. A receiver circuit as in claim 1 , wherein the first and second comparators each comprise a differential amplifier.
6. A receiver circuit as in claim 1 , wherein the first reference voltage corresponds to the lowest voltage of a logic HIGH signal.
7. A receiver circuit as in claim 1 , wherein the second reference voltage corresponds to the highest voltage of a logic LOW signal.
8. A method for receiving a data signal, comprising:
comparing the data signal with a first reference voltage to provide a first output signal representing a first detected state of the data signal, and simultaneously, comparing the data signal in a second comparator with a second reference voltage to provide a second output signal representing a second detected state of the data signal; and
detecting the first and second output signals and providing a third output signal, changing the logic state of the third output signal when the first and the second detected states agree, wherein
the first output signal is provided sooner than the second output signal when the data signal transitions to a first logic state, and
the second output signal is provided sooner than the first output signal when the data signal transitions to a second logic state opposite the first logic state.
9. A method as in claim 8 , further comprising providing a fourth output signal representing the earlier of the first and the second logic signals, in response to the data signal transition.
10. A method as in claim 9 , further comprising latching the fourth output signal.
11. A method as in claim 8 , wherein each of the comparing is performed by a differential amplifier.
12. A method as in claim 8 , wherein the first reference voltage corresponds to the lowest voltage of a logic HIGH signal.
13. A method as in claim 8 , wherein the second reference voltage corresponds to the highest voltage of a logic LOW signal.
14. A receiver circuit for a data signal, comprising:
a first stage receiving the data signal to provide a first output signal and a second output signal, the first output signal changing logic state sooner than the second output signal changing logic state when the data signal transitions to a first logic state, and the second output signal changing logic state sooner than the first output signal changing logic state when the data signal transitions to a second logic state opposite the first logic state; and
a second stage receiving the first and second output signals to provide a third output signal that changes logic state after both the first and second output signals changes logic state.
15. A receiver circuit as in claim 14 , further comprising a third stage receiving the first and second output signals and the third output signal to provide a fourth output signal, the fourth output signal changing logic state when the earlier of the first and second output signal changes logic state, and prior to the third output signal changes logic state.
16. A receiver circuit for a data signal, comprising:
in a first stage, means receiving the data signal for providing a first output signal and a second output signal, the first output signal changing logic state sooner than the second output signal changing logic state when the data signal transitions to a first logic state, and the second output signal changing logic state sooner than the first output signal changing logic state when the data signal transitions to a second logic state opposite the first logic state; and
in a second stage, means for receiving the first and second output signals for provide a third output signal that changes logic state after both the first and second output signals changes logic state.
17. A receiver circuit as in claim 16 , further comprising a third stage receiving the first and second output signals and the third output signal for provide a fourth output signal, the fourth output signal changing logic state when the earlier of the first and second output signal changes logic state, and prior to the third output signal changes logic state.