Patent Assignment
Reel/Frame 026794/0962
Corrective Assignment to Correct the Assignee Previously Recorded on Reel 020957 Frame 0434. Assignor(S) Hereby Confirms the Correct Assignees Are Sun Microsystems, Inc. and Sun Microsystems Technology Ltd.
Recorded: 2011-08-23
Pages: 8
Assignor
MONTALVO SYSTEMS, INC.
Executed: 2008-04-17
Assignees
SUN MICROSYSTEMS, INC.
4150 NETWORK CIRCLE, SANTA CLARA, CALIFORNIA, 95054
SUN MICROSYSTEMS TECHNOLOGY LTD.
CEDAR HOUSE, 41 CEDAR AVENUE, HAMILTON, HM12, BERMUDA
Covered Properties
(50)
Reducing Power Consumption for Processing of Common Values in Microprocessor Registers and Execution Units
Patent:
7,631,207 →
Application:
11/408,784 →
System and Method for Optimizing a Memory Controller
Patent:
7,627,730 →
Application:
11/416,872 →
System and Method for Conserving Power
Patent:
7,797,563 →
Application:
11/450,103 →
Cache Operations with Hierarchy Control
Patent:
7,539,819 →
Application:
11/543,598 →
Dynamic Resource Allocation Among Master Processors That Require Service from a Coprocessor
Synchronizing Master Processor by Stalling When Tracking of Coprocessor Rename Register Resource Usage Count for Sent Instructions Reaches Credited Apportioned Number
Coprocessor Receiving Renamed Register Identifier from Master to Complete an Operation Upon Register Data Ready
Small and Power-Efficient Cache That Can Provide Data for Background Dma Devices While the Processor Is in a Low-Power State
Power Conservation via Dram Access Reduction
Power Conservation via Dram Access
Maintaining Memory Coherency with a Trace Cache
Patent:
7,747,822 →
Application:
11/591,024 →
Prediction of Data Values Read from Memory by a Microprocessor Using the Storage Destination of a Load Operation
Patent:
7,788,473 →
Application:
11/646,008 →
Nand/Nor Registers
Dynamic Dual Output Latch
Enhanced Signaling Sensitivity Using Multiple References
Symmetrical Differential Amplifier
Memory Cells with Power Switch Circuit for Improved Low Voltage Operation
Virtual Core Management
Patent:
7,802,073 →
Application:
11/781,726 →
Trace Unit with a Decoder, A Basic-Block Builder, and a Multi-Block Builder
Application:
11/781,937 →
Method and System for Promoting Traces in an Instruction Processing Circuit
Application:
11/781,949 →
System and Method for Ensuring Coherency in Trace Execution
Patent:
8,032,710 →
Application:
11/782,163 →
Method and System for Utilizing a Common Structure for Trace Verification and Maintaining Coherency in an Instruction Processing Circuit
Patent:
8,015,359 →
Application:
11/782,238 →
Concurrent Vs. Low Power Branch Prediction
Patent:
7,966,479 →
Application:
11/880,859 →
Trace Unit with a Trace Builder
Patent:
7,949,854 →
Application:
11/880,861 →
Trace Unit with a Decoder, a Basic-Block Cache, a Multi-Block Cache, and Sequencer
Patent:
7,987,342 →
Application:
11/880,862 →
Trace Unit with an Op Path from a Decoder (Bypass Mode) and from a Basic-Block Builder
Patent:
7,953,961 →
Application:
11/880,863 →
Instruction Cache, Decoder Circuit, Basic Block Cache Circuit and Multi-Block Cache Circuit
Patent:
7,953,933 →
Application:
11/880,875 →
Trace Unit
Patent:
8,037,285 →
Application:
11/880,882 →
Graceful Degradation in a Trace-Based Processor
Patent:
7,783,863 →
Application:
11/923,638 →
Abort Prioritization in a Trace-Based Processor
Patent:
7,870,369 →
Application:
11/923,640 →
Dynamic Voltage Scaling for Self-Timed or Racing Paths
Method of Operating Memory Cell Providing Internal Power Switching
Patent:
7,626,853 →
Application:
11/932,738 →
Virtual Core Management
Patent:
8,219,788 →
Application:
11/933,267 →
Virtual Core Management
Patent:
7,797,512 →
Application:
11/933,297 →
Virtual Core Management
Patent:
8,225,315 →
Application:
11/933,319 →
Virtual Core Management
Patent:
8,543,843 →
Application:
11/933,349 →
Promoting and Appending Traces in an Instruction Processing Circuit Based Upon a Bias Value
Patent:
7,814,298 →
Application:
11/941,883 →
Flag Optimization of a Trace
Patent:
7,849,292 →
Application:
11/941,900 →
Emit Vector Optimization of a Trace
Patent:
7,937,564 →
Application:
11/941,908 →
Symbolic Renaming Optimization of a Trace
Patent:
8,499,293 →
Application:
11/941,912 →
Microprocessor Including a Display Interface in the Microprocessor
Patent:
9,336,752 →
Application:
11/963,579 →
Microprocessor Including a Display Interface in the Microprocessor
Patent:
8,890,876 →
Application:
11/963,603 →
Trace Based Deallocation of Entries in a Versioning Cache Circuit
Patent:
8,051,247 →
Application:
12/030,846 →
Memory Ordering Queue/Versioning Cache Circuit
Patent:
8,024,522 →
Application:
12/030,851 →
Trace Based Rollback of a Speculatively Updated Cache
Patent:
7,877,630 →
Application:
12/030,852 →
Data Cache Rollbacks for Failed Speculative Traces with Memory Operations
Patent:
8,370,609 →
Application:
12/030,854 →
Memory Ordering Queue Tightly Coupled with a Versioning Cache Circuit
Patent:
7,779,307 →
Application:
12/030,857 →
Cache Rollback Acceleration via a Bank Based Versioning Cache Circuit
Patent:
8,370,576 →
Application:
12/030,858 →
Rolling Back a Speculative Update of a Non-Modifiable Cache Line
Patent:
8,010,745 →
Application:
12/030,859 →
Checking for a Memory Ordering Violation After a Speculative Cache Write
Patent:
8,019,944 →
Application:
12/030,862 →
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.