Virtual core management

1. A virtual core management system comprising:

a physical core;

a first virtual core including a collection of logical states associated with execution of a first program, the first virtual core being mapped to the physical core;

a second virtual core including a collection of logical states associated with execution of a second program; and

a virtual core management component configured to both unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle,

wherein the virtual core management component is further configured to both unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is to executing an instruction in the first program that will cause the physical core to be idle for a time period exceeding a threshold, the instruction comprises an instruction corresponding to an input request or an output request that requires an acknowledgement by an input device or output device.

2. The virtual core management system of claim 1 , wherein the virtual core management component is further configured to map the second virtual core to the physical core in response to the virtual core management component also detecting that the second virtual core is ready to begin executing the second program.

3. The virtual core management system of claim 1 :

wherein the physical core includes registers,

wherein the virtual core management component is configured to unmap the first virtual core from the physical core by transferring one or more logical states of the first virtual core from the registers of the physical core to a memory external to the physical core, and

wherein map the second virtual core to the physical core by transferring one or more logical states of the second virtual core into the registers of the physical core.

4. A method adapted for use with a computer processor comprising a physical core, a first virtual core, and a second virtual core, the first virtual core including a collection of logical states associated with execution of a first program, the first virtual core being mapped to the physical core, the second virtual core including a collection of logical states associated with execution of a second program, the method comprising:

detecting that the physical core is idle;

unmapping the first virtual core from the physical core and mapping the second virtual core to the physical core in response to detecting that the physical core is idle;

detecting that the physical core is executing an instruction associated with the first program that will cause the physical core to be idle for a time period exceeding a threshold; and

unmapping the first virtual core from the physical core and mapping the second virtual core to the physical core in response to detecting that the physical core is executing an instruction associated with the first program that will cause the physical core to be idle for a time period exceeding a threshold, the instruction comprises an instruction corresponding to an input request or an output request that requires an acknowledgement by an input device or output device.

5. The method of claim 4 , wherein mapping the second virtual core to the physical core includes mapping the second virtual core to the physical core also in response to detecting that the second virtual core is ready to begin executing the second program.

6. The method of claim 4 , wherein:

the physical core includes registers;

unmapping the first virtual core from the physical core includes transferring one or more logical states of the first virtual core from the registers of the physical core to a memory external to the physical core; and

mapping the second virtual core to the physical core includes transferring one or more logical states of the second virtual core into the registers of the physical core.

7. A non-transitory computer readable medium that includes a circuit description of a virtual core management system, wherein the circuit description, when interpreted by a computer, specifies the virtual core management system comprising:

a physical core;

a first virtual core including a collection of logical states associated with execution of a first program, the first virtual core being mapped to the physical core;

a second virtual core including a collection of logical states associated with execution of a second program; and

a virtual core management component configured to both unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle,

wherein the virtual core management component is further configured to both unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is executing an instruction in the first program that will cause the physical core to be idle for a time period exceeding a threshold, the instruction comprises an instruction corresponding to an input request or an output request that requires an acknowledgement by an input device or output device.

8. A virtual core management system comprising:

a physical core;

a first virtual core including a collection of logical states associated with execution of a first program, the first virtual core being mapped to the physical core;

a second virtual core including a collection of logical states associated with execution of a second program;

means for unmapping the first virtual core from the physical core and mapping the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle; and

means for unmapping the first virtual core from the physical core and mapping the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is executing an instruction in the first program that will cause the physical core to be idle for a time period exceeding a threshold, the instruction comprises an instruction corresponding to an input request or an output request that requires an acknowledgement by an input device or output device.

9. A virtual core management system comprising:

a physical core;

a first virtual core including a collection of logical states associated with execution of a first program, the first virtual core being mapped to the physical core;

a second virtual core including a collection of logical states associated with execution of a second program; and

a virtual core management component configured to both unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle,

wherein the virtual core management component is further configured to both unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is executing an instruction in the first program that will cause the physical core to be idle for a time period exceeding a threshold, the instruction comprises an instruction corresponding to an input request or an output request that requires an acknowledgement by an input device or output device, and

wherein the collection of logical states includes a persistent micro-architectural state of the physical processor core and a transient micro-architectural state of the physical processor core.