Conductive materials for low resistance interconnects and methods of forming the same
Openings or features of small and large sizes are provided on a partially fabricated integrated circuit. The small openings are completely filled by electrodeposition of a first, low-resistivity material such as silver. The same deposition only partially fills the larger openings. A subsequent electrodeposition of a second metal, such as copper, fills the remainder of the larger features. While more highly resistive, the copper is much cheaper and resistivity is not as critical for these larger openings, which may represent bond pads or conductive lines, whereas the smaller features may represent more critical features such as small lines in an array for which high resistivity is more important, despite the expense.
1 . A method of depositing metal layers for an integrated circuit, comprising:
providing a substrate having a plurality of open first features and a plurality of open second features, wherein the second features have greater widths than the first features;
plating a first metal onto the substrate, the first metal completely filling the first features and only partially filling the second features; and
plating a second metal onto the first metal, the second metal filling unfilled portions of the second features, wherein the first metal has a lower resistivity than the second metal.
2 . The method of claim 1 , wherein the first metal comprises a noble metal.
3 . The method of claim 2 , wherein the first metal comprises silver and the second metal comprises copper.
4 . The method of claim 3 , wherein the second metal comprises a copper alloy.
5 . The method of claim 1 , wherein the first features have a width less than 100 nm.
6 . The method of claim 5 , wherein the first features have a width less than 65 nm.
7 . The method of claim 1 , wherein the second features comprise mid-size features having widths greater than 65 nm, and the second features further comprise large size features having widths greater than 1 micron.
8 . The method of claim 7 , wherein the large size features have widths larger than 5 microns.
9 . The method of claim 8 , wherein plating the first metal comprises lining the large features with the first metal.
10 . The method of claim 7 , wherein the mid-size features have widths larger than 100 mm.
11 . The method of claim 1 , wherein plating the first metal comprises electrochemical deposition.
12 . The method of claim 1 , wherein plating the second metal comprises electrochemical deposition.
13 . A process for filling features on a substrate for semiconductor fabrication, the process comprising:
providing a substrate having an insulating layer with the features formed therein, the features including small features having widths of less than 100 nm and larger features having a width greater than the widths of the small features;
depositing a first metal into the larger and small features, the first metal completely filling the small features and partially filling the larger features; and
depositing a second metal directly onto the first metal, the second metal filling a remaining unfilled portion of the larger features and having a conductivity less than a conductivity of the first metal.
14 . The process of claim 13 , wherein the first metal comprises a noble metal.
15 . The process of claim 14 , wherein the first metal comprises silver.
16 . The method of claim 13 , wherein the first metal has a resistivity lower than 1.725 μΩ·cm at 300 K.
17 . The process of claim 16 , wherein the second metal comprises copper.
18 . The process of claim 17 , wherein the second metal comprises a copper alloy.
19 . The process of claim 13 , wherein depositing the first metal comprises plating.
20 . The process of claim 19 , wherein depositing the first metal comprises electrochemical deposition.
21 . The process of claim 13 , wherein depositing the second metal comprises plating.
22 . The process of claim 21 , wherein depositing the second metal comprises electrochemical deposition.
23 . The process of claim 13 , wherein the larger features comprise a plurality of mid-size features having widths greater than 65 nm and a plurality of larger size features having widths greater than 1 micron.
24 . The process of claim 23 , wherein the larger size features have widths greater than 5 microns.
25 . The process of claim 23 , wherein the mid-size features have widths greater than 100 nm.
26 - 33 . (canceled)
34 . A method of filling features on a surface of a wafer, comprising:
filling features with a first conductor having a first conductivity, the first conductor completely filling features having less than 100 nm width while partially filling features having more than 100 nm width; and
depositing a second conductor having a second conductivity less than the first conductivity onto the first conductor to completely fill the features having more than 100 nm width.
35 . The method of claim 34 , wherein filling forms a first conductor layer on the surface of the wafer.
36 . The method of claim 34 , wherein depositing forms a second conductor layer on the surface of the wafer.
37 . The method of claim 34 , wherein filling comprises electrochemical deposition.
38 . The method of claim 34 , wherein filling comprises chemical vapor deposition.
39 . The method of claim 34 , wherein filling comprises electroless deposition.
40 . The method of claim 34 , wherein depositing comprises electrochemical deposition.
41 . The method of claim 34 , wherein depositing comprises chemical vapor deposition.
42 . The method of claim 34 , wherein depositing comprises electroless deposition.
43 . The method of claim 34 , wherein the first conductor is silver.
44 . The method of claim 34 , wherein the second conductor is copper.
45 . The method of claim 34 , wherein the first conductor comprises a superconductive material.