Optimized circuits for three dimensional packaging and methods of manufacture therefore

1. An apparatus, comprising:

an integrated circuit, wherein a first portion of said integrated circuit is placed on a top tier substrate and a second portion of said integrated circuit is placed on a bottom tier substrate stacked adjacent said top tier substrate and wherein said first portion and said second portion of said integrated circuit are interconnected; and

printed spiral arms stacked vertically on both the top and bottom surface of said top tier substrate thereby creating high Q inductors;

wherein said first portion of said integrated circuit includes at least the following components:

at least one output match;

at least one harmonic filter; and

at least one interconnect to said second portion of said integrated circuit on said second substrate; and

wherein said second portion of said integrated circuit includes at least the following components:

at least one power amplifier;

at least one bias and power controller connected to said at least one power amplifier;

at least one antenna switch connected to said at least one bias and power controller; and

at least one interconnect to said first portion of said integrated circuit.

2. The apparatus of claim 1 , wherein said top tier substrate is comprised of low dielectric material.

3. The apparatus of claim 2 , wherein a distance between said top tier and said bottom tier substrate is sufficiently large to facilitate high impedance functions and components.

4. The apparatus of claim 2 , further comprising printing inductors on said top tier substrate thereby enabling them to be high Q inductors.

5. The apparatus of claim 1 , wherein said high Q inductor is further connected to the top surface of said bottom tier substrate.

6. The apparatus of claim 1 , wherein critical and difficult to design RF functions and building blocks are placed on said top tier substrate due to ease of access.

7. The apparatus of claim 1 , wherein said top tier and said bottom tier substrates have distinct dielectric constants with different heights from a ground plane associated with said first-and second portions of said circuit.

8. The apparatus of claim 1 , further comprising placing components and functions on the top tier and bottom tier substrates so as to minimize z-axis interconnects and maximize performance.

9. The apparatus of claim 1 , further comprising placing components and functions on the top tier and bottom tier substrates to maximize the ability to tune critical parts of said circuit.

10. The apparatus of claim 1 , wherein said second portion of said integrated circuit includes at least the following components:

at least one power amplifier;

at least one bias and power controller connected to said at least one power amplifier;

at least two antenna switches connected to said at least one bias and power controller and further connected to an antenna via a diplexer; and

at least one interconnect to said first portion of said integrated circuit.

11. A method, comprising:

placing a first portion of said integrated circuit on a top tier substrate;

placing a second portion of an integrated circuit on a bottom tier substrate that stacked adjacent said top tier substrate;

stacking printed spiral arms vertically on both the top and bottom surface of said top tier substrate thereby creating high Q inductors; and

interconnecting said first portion and said second portion of said integrated circuit;

wherein said first portion of said integrated circuit includes at least the following components:

at least one output match;

at least one harmonic filter; and

at least one interconnect to said second portion of said integrated circuit on said second substrate; and

wherein said second portion of said integrated circuit includes at least the following components:

at least one power amplifier;

at least one bias and power controller connected to said at least one power amplifier;

at least one antenna switch connected to said at least one bias and power controller; and

at least one interconnect to said first portion of said integrated circuit.

12. The method of claim 11 , further comprising placing said top tier and said bottom tier substrate at a predetermined distance that enables high impedance functions and components.

13. The method of claim 12 , further comprising using distinct dielectric constants with different heights from a ground plane by said top tier and said bottom tier substrates associated with said first and second portions of said circuit.

14. The method of claim 11 , further comprising placing critical and difficult to design RF functions and building blocks on said top tier substrate due to ease of access.

15. The method of claim 11 , further comprising placing components and functions on the top tier and bottom tier substrates to minimize z-axis interconnects and maximize performance.

16. The method of claim 11 , further comprising placing at least the following components on said second portion of said integrated circuit:

at least one power amplifier;

at least one bias and power controller connected to said at least one power amplifier;

at least two antenna switches connected to said at least one bias and power controller and further connected to an antenna via a diplexer; and

at least one interconnect to said first portion of said integrated circuit on said first substrate.