Technique for determining performance characteristics of electronic devices and systems
View Patent ↗A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.
1. A method for determining worst case bit sequences, the method comprising the steps of:
acquiring a first representation of a first response on a first signal line resulting from a first signal transmitted on the first signal line;
acquiring a second representation of a second response on the first signal line resulting from at least one second signal transmitted on at least one second signal line, the at least one second signal line being substantially adjacent to the first signal line; and
generating worst case bit sequences based upon the first representation of the first response and the second representation of the second response for transmission on the first signal line and the at least one second signal line for use in determining performance characteristics associated with at least the first signal line;
wherein generating worst case bit sequences comprises generating worst case timing margin bit sequences and worst case voltage margin bit sequences for transmission on the first signal line and the at least one second signal line, wherein generating worst case timing margin bit sequences for transmission on the first signal line comprises determining a polarity of the first response at data-cell boundaries of the first response, wherein if the polarity at a data-cell boundary is positive, then an associated bit in a first worst case timing margin bit sequence for transmission on the first signal line is assigned a logic one value, and wherein if the polarity at a data-cell boundary is negative, then an associated bit in the first worst case timing margin bit sequence for transmission on the first signal line is assigned a logic zero value.
2. The method of claim 1 , wherein the polarity is measured against a reference value.
3. The method of claim 2 , wherein if the polarity at a data-cell boundary is positive, then an associated bit in a complementary worst case timing margin bit sequence for transmission on the first signal line is assigned a logic zero value, and wherein if the polarity at a data-cell boundary is negative, then an associated bit in a complementary worst case timing margin bit sequence for transmission on the first signal line is assigned a logic one value.
4. The method of claim l, wherein generating worst case timing margin bit sequences for transmission on the at least one second signal line comprises the step of:
determining a polarity of the second response at data-cell boundaries of the second response, wherein the polarity is measured against a reference value.
5. The method of claim 4 , wherein if the polarity at a data-cell boundary is positive, then an associated bit in a first worst case timing margin bit sequence for transmission on the at least one second signal line is assigned a logic one value, and wherein if the polarity at a data-cell boundary is negative, then an associated bit in the first worst case timing margin bit sequence for transmission on the at least one second signal line is assigned a logic zero value.
6. The method of claim 5 , wherein if the polarity at a data-cell boundary is positive, then an associated bit in a complementary worst case timing margin bit sequence for transmission on the at least one second signal line is assigned a logic zero value, and wherein if the polarity at a data-cell boundary is negative, then an associated bit in a complementary worst case timing margin bit sequence for transmission on the at least one second signal line is assigned a logic one value.
7. The method of claim 1 , wherein generating worst case voltage margin bit sequences for transmission on the first signal line comprises the step of:
determining a polarity of the first response at the center of data-cells of the first response, wherein the polarity is measured against a reference value.
8. The method of claim 7 , wherein if the polarity at the center of a data-cell is positive, then an associated bit in a first worst case voltage margin bit sequence for transmission on the first signal line is assigned a logic one value, and wherein if the polarity at the center of a data-cell is negative, then an associated bit in the first worst case voltage margin bit sequence for transmission on the first signal line is assigned a logic zero value.
9. The method of claim 8 , wherein if the polarity at the center of a data-cell is positive, then an associated bit in a complementary worst case voltage margin bit sequence for transmission on the first signal line is assigned a logic zero value, and wherein if the polarity at the center of a data-cell is negative, then an associated bit in a complementary worst case voltage margin bit sequence for transmission on the first signal line is assigned a logic one value.
10. The method of claim l, wherein generating worst case voltage margin bit sequences for transmission on the at least one second signal line comprises the step of:
determining a polarity of the second response at the center of data-cells of the second response, wherein the polarity is measured against a reference value.
11. The method of claim 10 , wherein if the polarity at the center of a data-cell is positive, then an associated bit in a first worst case voltage margin bit sequence for transmission on the at least one second signal line is assigned a logic one value, and wherein if the polarity at the center of a data-cell is negative, then an associated bit in the first worst case voltage margin bit sequence for transmission on the at least one second signal line is assigned a logic zero value.
12. The method of claim 11 , wherein if the polarity at the center of a data-cell is positive, then an associated bit in a complementary worst case voltage margin bit sequence for transmission on the at least one second signal line is assigned a logic zero value, and wherein if the polarity at the center of a data-cell is negative, then an associated bit in a complementary worst case voltage margin bit sequence for transmission on the at least one second signal line is assigned a logic one value.