Patent Assignment
Reel/Frame 058956/0139
Assignment of Assignor's Interest
Recorded: 2021-12-10
Pages: 13
Assignor
HIGHLANDS LLC
Executed: 2021-12-01
Assignee
RAMPART ASSET MANAGEMENT, LLC
5900 BALCONES DRIVE, SUITE 100, AUSTIN, TEXAS, 78731
Covered Properties
(90)
Method and Apparatus for Evaluating and Optimizing a Signaling System
PCT:
PCT/US2002/032602 ↗
Method and Apparatus for Evaluating and Calibrating a Signaling System
Patent:
6,873,939 →
Application:
09/776,550 →
Technique for Determining Performance Characteristics of Electronic Devices and Systems
Patent:
6,920,402 →
Application:
09/799,516 →
Mechanism for Enabling Full Data Bus Utilization Without Increasing Data Granularity
Patent:
7,500,075 →
Application:
09/837,307 →
Method and Apparatus for Coordinating Memory Operations Among Diversely-Located Memory Components
Configurable Addressing for Multiple Chips in a Package
Patent:
6,657,914 →
Application:
09/909,675 →
Clock Data Recovery with Selectable Phase Control
Patent:
7,099,424 →
Application:
09/941,079 →
Method and Apparatus for Evaluating and Optimizing a Signaling System
Method and Apparatus for Signaling Between Devices of a Memory System
Selectable-Tap Equalizer
Timing Calibration Apparatus and Method for a Memory Device Signaling System
Phase Adjustment Apparatus and Method for a Memory Device Signaling System
Method and Apparatus for Coordinating Memory Operations Among Diversely-Located Memory Components
Technique for Determining Performance Characteristics of Electronic Devices and Systems
Patent:
7,006,932 →
Application:
10/954,489 →
Memory Device Signaling System and Method with Independent Timing Calibration for Parallel Signal Paths
Memory Device with Clock Multiplier Circuit
Memory Module with Termination Component
Memory Module with Termination Component
Memory Module with Termination Component
Method, System and Memory Controller Utilizing Adjustable Write Data Delay Settings
Method, System and Memory Controller Utilizing Adjustable Read Data Delay Settings
Technique for Determining Performance Characteristics of Electronic Devices and Systems
Method and Apparatus for Evaluating and Optimizing a Signaling System
Method and Apparatus for Evaluating and Optimizing a Signaling System
Method and Apparatus for Evaluating and Optimizing a Signaling System
Application:
11/686,706 →
Publication:
US 2007/0165472
Memory Controller Device Having Timing Offset Capability
Clocked Memory System with Termination Component
Phase Adjustment Apparatus and Method for a Memory Device Signaling System
Selectable-Tap Equalizer
Memory Module with Termination Component
Selectable-Tap Equalizer
Selectable-Tap Equalizer
Selectable-Tap Equalizer
Method and Apparatus for Signaling Between Devices of a Memory System
Mechanism for Enabling Full Data Bus Utilization Without Increasing Data Granularity
Selectable-Tap Equalizer
Technique for Determining Performance Characteristics of Electronic Devices and Systems
Method and Apparatus for Evaluating and Optimizing a Signaling System
Phase Adjustment Apparatus and Method for a Memory Device Signaling System
Technique for Determining Performance Characteristics of Electronic Devices and Systems
Method and Apparatus for Evaluating and Optimizing a Signaling System
Selectable-Tap Equalizer
Memory Controller
Memory Controller with Selective Data Transmission Delay
Mechanism for Enabling Full Data Bus Utilization Without Increasing Data Granularity
Selectable-tap Equalizer
Memory Module
Method And Apparatus For Evaluating And Optimizing A Signaling System
Method and Apparatus for Evaluating and Optimizing a Signaling System
Technique for Determining Performance Characteristics Of Electronic Devices And Systems
Memory Component with Terminated and Unterminated Signaling Inputs
Memory Component that Samples Command/Address Signals in Response to Both Edges of a Clock Signal
Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration
Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration
Memory Controller That Enforces Strobe-to-Strobe Timing Offset
Selectable-tap Equalizer
Application:
14/145,960 →
Publication:
US 2014/0286383
Method And Apparatus For Evaluating And Optimizing A Signaling System
Mechanism for Enabling Full Data Bus Utilization Without Increasing Data Granularity
Memory Module
Selectable-tap Equalizer
Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration
Selectable-tap Equalizer
Mechanism for Enabling Full Data Bus Utilization Without Increasing Data Granularity
Memory Controller
Method And Apparatus For Evaluating And Optimizing A Signaling System
Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration
Mechanism for Enabling Full Data Bus Utilization Without Increasing Data Granularity
Selectable-tap Equalizer
Memory Controller
Technique for Determining Performance Characteristics Of Electronic Devices And Systems
Selectable-tap Equalizer
Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration
Memory Controller
Selectable-tap Equalizer
Technique for Determining Performance Characteristics Of Electronic Devices And Systems
Selectable-Tap Equalizer
Mechanism for Enabling Full Data Bus Utilization Without Increasing Data Granularity
Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration
Memory Controller
Selectable-tap Equalizer
Selectable-tap Equalizer
Memory Controller
Application:
16/896,056 →
Publication:
US 2021/0027825
Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration
Selectable-tap Equalizer
Yellowstone technology report preliminary (cover page, table of contents, chapter 4, 5 and 6)
Application:
60/343,905 →
Timing calibration apparatus and method for a memory device signaling system
Application:
60/376,947 →
Method, System and Memory Controller Utilizing Adjustable Write Data Delay Settings
Application:
90/009,357 →
Method, System and Memory Controller Utilizing Adjustable Read Data Delay Settings
Application:
90/009,358 →
Method, System and Memory Controller Utilizing Adjustable Read Data Delay Settings
Application:
95/001,159 →
Method, System and Memory Controller Utilizing Adjustable Write Data Delay Settings
Application:
95/001,160 →
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 28, 2009
From: INAPAC TECHNOLOGY, INC.
To: RAMBUS INC.
Reel/Frame 022597/0896 →
Assignment of Assignor's Interest
Nov 3, 2014
From: WARE, FREDERICK A.; TSERN, ELY K.; PEREGO, RICHARD E.; HAMPEL, CRAIG E.
To: RAMBUS INC.
Reel/Frame 034093/0933 →
Assignment of Assignor's Interest
Dec 14, 2016
From: WARE, FREDERICK A.; TSERN, ELY K.; PEREGO, RICHARD E.; HAMPEL, CRAIG E.
To: RAMBUS INC.
Reel/Frame 040732/0710 →
Assignment of Assignor's Interest
Feb 28, 2017
From: LIAW, HAW-JYH; YUAN, XINGCHAO; HOROWITZ, MARK
To: RAMBUS INC.
Reel/Frame 041397/0745 →
Assignment of Assignor's Interest
Dec 2, 2021
From: RAMBUS INC.
To: HIGHLANDS LLC
Reel/Frame 058298/0836 →