Mechanism for enabling full data bus utilization without increasing data granularity
View Patent ↗A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.
1. A memory device, comprising:
at least two electrically isolated memory portions, each portion including banks of memory and circuitry to write and read data to the respective bank in association with memory write and read transactions;
interface circuitry to receive commands and to exchange the write and read data external to the apparatus in association with the memory write and read transactions; and
logic to identify based on the commands one of the at least two electrically isolated portions that is the target of each transaction of the memory write and read transactions, and to route said each write and read transaction to said target;
wherein each given portion of the at least two electrically isolated portion is characterized by a timing constraint that must elapse between row activations within the given portion, and wherein the memory device is characterized as having no timing constraint imposed on when a first portion of the at least two electrically isolated portions can be accessed relative to a second portion of the at least two electrically isolated portions.
2. The memory device of claim 1 , wherein:
the memory device is to receive serialized packets comprising command information for each transaction; and
the command information comprises a portion indication and memory address information.
3. The memory device of claim 1 , wherein:
each transaction of the memory write and read transactions is commanded using address information comprising a portion indication, row address information and column address information; and
the address information is received via at least one external link in a manner not separated by idle time consisting of one or more clock cycles.
4. The memory device of claim 3 , wherein each of the banks comprise dynamic random access memory (DRAM) cells.
5. The memory device of claim 4 , wherein the timing constraint that must elapse between row activations within each given portion is Trr.
6. The memory device of claim 1 , wherein each given portion of the at least two electrically isolated portions is isolated in a manner that sense amplifier activation for a bank in the given portion does not corrupt concurrent data access in another portion of the at least two electrically isolated portions.
7. The memory device of claim 1 , wherein the memory device is to receive the commands via plural communication links external to the memory device.
8. The memory device of claim 1 , wherein the memory device is to receive both row command and column command information in multiplexed fashion over a single set of external control lines.
9. The memory device of claim 8 , wherein the memory device is to receive both a row command and a column command within an interval no greater than time needed to cycle column access circuitry once for one of the banks.
10. The memory device of claim 1 , wherein the memory device is to substantially concurrently receive row command information and column command information as part of an exchange with an external device.
11. The memory device of claim 10 , wherein the row command information and column command information received as part of the exchange correspond to different write or read transactions.
12. The memory device of claim 11 , where the different write or read transactions are directed to different portions of the at least two electrically isolated portions.
13. A memory device, comprising:
at least two electrically isolated memory portions, each portion including banks of memory and circuitry to write and read data to the respective bank in association with memory write and read transactions;
interface circuitry to receive commands and to exchange the write and read data external to the apparatus in association with the memory write and read transactions; and
logic to identify based on the commands one of the at least two electrically isolated portions that is the target of each transaction of the memory write and read transactions, and to route said each write and read transaction to said target;
wherein the memory device is to receive serialized packets comprising command information for each transaction, and each exchange of command information with an external device comprises a portion indication and memory address information, wherein each given portion of the at least two electrically isolated portion is characterized by a timing constraint that must elapse between row activations within the given portion, and wherein the memory device is characterized as having no timing constraint imposed on when a first portion of the at least two electrically isolated portions can be accessed relative to a second portion of the at least two electrically isolated portions.
14. The memory device of claim 13 , wherein:
each of the banks comprise dynamic random access memory (DRAM) cells; and
each given portion of the at least two electrically isolated portion is characterized by a the timing constraint, Trr, that must elapse between row activations within each given portion is Trr.
15. The memory device of claim 13 , wherein each given portion of the at least two electrically isolated portions is isolated in a manner that sense amplifier activation for a bank in the given portion does not corrupt concurrent data access in another portion of the at least two electrically isolated portions.
16. A memory device, comprising:
at least two electrically isolated memory portions, each portion including banks of memory and circuitry to write and read data to the respective bank in association with memory write and read transactions;
interface circuitry to receive commands and exchange the write and read data external to the apparatus in association with the memory write and read transactions, wherein commands for each transaction of the memory write and read transactions comprise a portion indication, row control information and column control information, received in a manner not separated by idle time consisting of one or more clock cycles; and
logic to identify based on the commands one of the at least two electrically isolated portions that is the target of each transaction of the memory write and read transactions, and to route said each write and read transaction to said target;
wherein each given portion of the at least two electrically isolated portion is characterized by a timing constraint that must elapse between row activations within the given portion, and wherein the memory device is characterized as having no timing constraint imposed on when a first portion of the at least two electrically isolated portions can be accessed relative to a second portion of the at least two electrically isolated portions.
17. The memory device of claim 16 , wherein the memory device is to receive the commands for each transaction in the form of serialized packets from an external device.
18. The memory device of claim 16 , wherein:
each of the banks comprise dynamic random access memory (DRAM) cells; and
each given portion of the at least two electrically isolated portions is characterized by a the timing constraint that must elapse between row activations within each given portion is Trr.
19. The memory device of claim 16 , wherein the memory device is to receive the commands via plural communication links external to the memory device.