Selectable-tap equalizer

1. An integrated circuit receiver to receive an input signal from a conductive signal path, comprising:

a clock recovery circuit to generate an edge clock;

circuitry to generate a data clock and an equalization clock, each of the data clock and the equalization clock being phase-offset relative to the edge clock;

a sampling circuit to sample the input signal and generate digital samples according to the data clock; and

an equalization circuit to equalize the input signal, in dependence on at least one preceding digital sample, according to the equalization clock; and

wherein during a calibration mode,

the integrated circuit receiver is to lock the edge clock against phase adjustment,

the equalization circuit is to drive a data pattern onto the conductive signal path according to the equalization clock,

the clock recovery circuit is to generate phase adjustments which track transitions in the data pattern relative to the edge clock, and

the circuitry to generate is to adjust the equalization clock responsive to the phase adjustments which track the transitions in the data pattern until the transitions in the data pattern align with the edge clock, to thereby establish the phase-offset of the equalization clock relative to the edge clock for use in a normal operating mode.

2. The integrated circuit receiver of claim 1 , wherein the equalization circuit comprises an equalizing driver, and wherein the phase-offset of the equalization clock relative to the edge clock is dependent upon a delay of the equalizing driver in driving the data pattern onto the conductive signal path.

3. The integrated circuit receiver of claim 2 , wherein during the calibration mode the equalization circuit is to drive the data pattern onto the conductive signal path in absence of the input signal on the conductive signal path.

4. The integrated circuit receiver of claim 1 , wherein:

the integrated circuit receiver further comprises circuitry to determine an equalization symbol latency during the calibration mode; and

the equalization circuit is to equalize the input signal during the normal operating mode according to each of the at least one preceding digital sample, the equalization symbol latency determined during the calibration mode and the phase-offset of the equalization clock relative to the edge clock determined during the calibration mode.

5. The integrated circuit receiver of claim 4 , wherein the integrated circuit receiver comprises a shift register to receive the digital samples, in sequence, and a tap data source selector, and wherein the integrated circuit receiver is to apply the equalization symbol latency to the tap data source selector to provide a digital sample from the shift register which corresponds to a selected latency to the equalization circuit.

6. The integrated circuit receiver of claim 1 , further comprising a first mixer circuit to generate at least one of the edge clock or the data clock as a first interpolated clock, and a second mixer circuit to generate the equalization clock as a second interpolated clock, each interpolated clock having a common frequency but respective phase.

7. The integrated circuit receiver of claim 1 , wherein the input signal is a double data rate (DDR) signal, and wherein the sampling circuit is to sample the input signal at a frequency corresponding to the maximum rate of value change of symbols carried by the input signal.

8. The integrated circuit receiver of claim 1 , wherein the input signal conveys multi-bit digital symbols, and wherein the sampling circuit comprises at least two samplers, each sampler to sample according to the data clock a respective bit of information from a common digital symbol carried by the input signal.

9. A method of operating an integrated circuit receiver, the method comprising:

using a clock recovery circuit to generate an edge clock;

generating a data clock and an equalization clock, each in a manner that is phase-offset relative to the edge clock;

sampling an input signal from a conductive signal path and generating digital samples according to the data clock; and

equalizing the input signal in dependence on at least one preceding digital sample according to the equalization clock; and

wherein the method further comprises establishing the phase-offset of the equalization clock by, during a calibration mode,

locking the edge clock against phase adjustment,

driving a data pattern onto the conductive signal path according to the equalization clock,

using the clock recovery circuit to generate phase adjustments which track transitions in the data pattern relative to the edge clock, and

generating is to adjust the equalization clock responsive to the phase adjustments which track the transitions in the data pattern until the transitions in the data pattern align with the edge clock, to thereby establish the phase-offset of the equalization clock relative to the edge clock; and

wherein the method further comprises applying in a normal operating mode the phase-offset determined during the calibration mode.

10. The method of claim 9 , wherein equalizing comprises operating an equalization driver to drive an equalization signal onto the conductive signal path, and wherein the phase-offset of the equalization clock relative to the edge clock is dependent upon a delay of the equalizing driver in driving the data pattern onto the conductive signal path.

11. The method of claim 10 , wherein during the calibration mode the equalization driver is to drive the data pattern onto the conductive signal path in absence of the input signal on the conductive signal path.

12. The method of claim 9 , wherein:

the method further comprises determining an equalization symbol latency during the calibration mode; and

equalizing comprises equalizing equalize the input signal during the normal operating mode according to each of the at least one preceding digital sample, the equalization symbol latency determined during the calibration mode and the phase-offset of the equalization clock relative to the edge clock determined during the calibration mode.

13. The method of claim 12 , wherein the integrated circuit receiver comprises a shift register to receive the digital samples, in sequence, and a tap data source selector, and wherein the method further comprises applying the equalization symbol latency to the tap data source selector to provide a digital sample from the shift register which corresponds to a selected latency.

14. The method of claim 9 , wherein the method further comprises using a first mixer circuit to generate at least one of the edge clock or the data clock as a first interpolated clock, and using a second a second mixer circuit to generate the equalization clock as a second interpolated clock, in a manner where each interpolated clock is generated to have a common frequency but respective phase.

15. The method of claim 9 , wherein the input signal is a double data rate (DDR) signal, and wherein sampling comprises sampling the input signal at a frequency corresponding to the maximum rate of value change of symbols carried by the input signal.

16. The method of claim 9 , wherein the input signal conveys multi-bit digital symbols, and wherein sampling comprises using at least two samplers to concurrently sample the input signal, each sampler to sample a respective bit of information from a common digital symbol carried by the input signal.

17. An integrated circuit receiver to receive an input signal from a conductive signal path, comprising:

a clock recovery circuit to generate an edge clock;

means for generating a data clock and an equalization clock, each in a manner that is phase-offset relative to the edge clock;

means for sampling an input signal from a conductive signal path and generating digital samples according to the data clock; and

means for equalizing the input signal in dependence on at least one preceding digital sample according to the equalization clock; and

wherein the integrated circuit receiver further comprises means for, during a calibration mode, locking the edge clock against phase adjustment,

driving a data pattern onto the conductive signal path according to the equalization clock,

using the clock recovery circuit to generate phase adjustments which track transitions in the data pattern relative to the edge clock, and

adjusting the equalization clock responsive to the phase adjustments which track the transitions in the data pattern until the transitions in the data pattern align with the edge clock, to thereby establish the phase-offset of the equalization clock relative to the edge clock; and

wherein the integrated circuit receiver is to apply in a normal operating mode the phase-offset determined during the calibration mode.