Technique for determining performance characteristics of electronic devices and systems
A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.
1. A method of determining a performance characteristic of a signaling system, comprising:
causing a receiver circuit of the signaling system to measure, on a first transmission path of the signaling system, a first time-varying response to a signal transmitted on a second transmission path of the signaling system;
causing the receiver circuit to measure, on the first transmission path, a second time-varying response to a signal transmitted on the first transmission path; and
identifying the performance characteristic dependent on the first time-varying response and the second time-varying response.
2. The method of claim 1 , wherein the signal transmitted on the first transmission path comprises a single pulse, and wherein causing the receiver circuit to measure the first time-varying response comprises causing the receiver circuit to sample the first transmission path at least thrice at respective times that span more than one data-cell interval to obtain the first time-varying response.
3. The method of claim 2 , wherein identifying the performance characteristic comprises determining a worst case timing margin bit sequence, and wherein causing the receiver circuit to sample at least thrice comprises sampling the first transmission path at three respective data-cell boundaries to obtain the first time-varying response.
4. The method of claim 2 , wherein identifying the performance characteristic comprises determining a worst case voltage margin bit sequence, and wherein causing the receiver circuit to sample at least thrice comprises sampling the first transmission path at times intermediate to three respective data-cells to obtain the first time-varying response.
5. The method of claim 1 , wherein the signal transmitted on the second transmission path comprises a single pulse, and wherein causing the receiver circuit to measure the second time-varying response comprises causing the receiver circuit to sample the first transmission path at least thrice at respective times that span more than one data-cell interval to obtain the second time-varying response.
6. The method of claim 5 , wherein identifying the performance characteristic comprises determining a worst case timing margin bit sequence, and wherein causing the receiver circuit to sample at least thrice comprises sampling the first transmission path at three respective data-cell boundaries to obtain the second time-varying response.
7. The method of claim 5 , wherein identifying the performance characteristic comprises determining a worst case voltage margin bit sequence, and wherein causing the receiver circuit to sample at least thrice comprises sampling the first transmission path at times intermediate to three respective data-cells to obtain the second time-varying response.
8. The method of claim 1 , wherein the receiver circuit comprises an analog-to-digital converter circuit and wherein causing a receiver circuit to measure the first time-varying response and causing the receiver circuit to measure the second time-varying response each comprise producing a set of bits with the analog-to-digital converter circuit, the set representing sampled voltage present on the first transmission path.
9. The method of claim 1 , wherein the receiver circuit is embodied on an IC device comprising a memory array, and wherein the receiver circuit is to receive data from the first transmission path for storage in the memory array during a normal mode of operation.
10. The method of claim 1 , wherein the performance characteristic comprises a worst case combination of bit patterns respectively transmitted on the first transmission path and the second transmission path.
11. An apparatus for determining a performance characteristic of a signaling system, comprising:
a receiver circuit of the signaling system to measure, on a first transmission path of the signaling system, a first time-varying response to a signal transmitted on a second transmission path of the signaling system, and a second time-varying response to a signal transmitted on the first transmission path; and
a processor to identify the performance characteristic dependent on the first time-varying response and the second time-varying response.
12. The apparatus of claim 11 , wherein the signal transmitted on the first transmission path comprises a single pulse, and wherein the receiver circuit is to sample the first transmission path at least thrice at respective times that span more than one data-cell interval to obtain the first time-varying response.
13. The apparatus of claim 12 , wherein the processor is to identify a worst case timing margin bit sequence, and wherein the receiver circuit is to sample the first transmission path at three respective data-cell boundaries to obtain the first time-varying response.
14. The apparatus of claim 12 , wherein the processor is to identify a worst case voltage margin bit sequence, and wherein the receiver circuit is to sample the first transmission path at times intermediate to three respective data-cells to obtain the first time-varying response.
15. The apparatus of claim 11 , wherein the signal transmitted on the second transmission path comprises a single pulse, and wherein the receiver circuit is to sample the first transmission path at least thrice at respective times that span more than one data-cell interval to obtain the second time-varying response.
16. The apparatus of claim 15 , wherein the processor is to identify a worst case timing margin bit sequence, and wherein the receiver circuit is to sample the first transmission path at three respective data-cell boundaries to obtain the second time-varying response.
17. The apparatus of claim 15 , wherein the processor is to identify a worst case voltage margin bit sequence, and wherein the receiver circuit is to sample the first transmission path at times intermediate to three respective data-cells to obtain the second time-varying response.
18. The apparatus of claim 11 , wherein the receiver circuit comprises an analog-to-digital converter circuit to produce a set of bits for each measurement, the set representing sampled voltage present on the first transmission path.
19. The apparatus method of claim 11 , wherein the receiver circuit is embodied on an IC device comprising a memory array, and wherein the receiver circuit is to receive data from the first transmission path for storage in the memory array during a normal mode of operation.
20. The apparatus of claim 11 , wherein the performance characteristic comprises a worst case combination of bit patterns respectively transmitted on the first transmission path and the second transmission path.