Technique for determining performance characteristics of electronic devices and systems
A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.
1. A receiver integrated circuit, comprising:
data receivers to receive data over respective transmission lines of a digital bus of a signaling system from a transmitter integrated circuit of the signaling system, the data receivers including at least one circuit to compare;
wherein, in a test mode, a first one of the data receivers is to sample its respective transmission line in the signaling system as a victim line in the presence of cross talk contributed to the victim line from a test signal transmitted over one or more others of the transmission lines as aggressor lines; and
wherein the at least one circuit to compare is to generate an output responsive to the sampling by the first one of the data receivers of its respective one of the transmission lines in the signaling system to measure a performance characteristic of the signaling system as a function of the cross talk.
2. The receiver integrated circuit of claim 1 , wherein the at least one circuit to compare comprises a circuit to compare for each of the data receivers, wherein during the test mode each of the data receivers including the first one is to sample, at respective times relative to the other data receivers, its respective transmission line as a victim line in the presence of cross talk contributed to the victim line from a test signal transmitted over one or more others of the other transmission lines as aggressor lines, and wherein the circuit to compare for each of the receivers is to generate a corresponding output responsive to sampling by the corresponding receiver of its respective transmission line in the signaling system to measure a performance characteristic of the signaling system as a function of the cross talk.
3. The receiver integrated circuit of claim 1 , wherein the circuit to compare further comprises circuitry to provide a multiplied clock for sampling of the victim line during the test mode so as to capture samples at a rate that is faster than a rate at which data is transmitted on the respective transmission line.
4. The receiver integrated circuit of claim 1 , wherein transmitters for at least two of the aggressor lines are to transmit in parallel a test signal to the receiver integrated circuit and a transmitter for the victim line is to remain inactive while the first one of the data receivers samples its respective transmission line.
5. The receiver integrated circuit of claim 1 , wherein during the test mode, a transmitter for the victim line is to transmit a test signal while the first one of the data receivers samples its respective transmission line to measure a performance characteristic of the signaling system dependent on reflection interference on the victim line.
6. The receiver integrated circuit of claim 1 , where the test signal is common and concurrent for each of at least two of the other transmission lines as aggressor lines.
7. The receiver integrated circuit of claim 1 , wherein at least one test signal transmitted to the receiver integrated circuit over an aggressor line is a single unit pulse, and wherein the receiver integrated circuit is to capture multiple samples of the victim line to measure crosstalk generated as a result of the single unit pulse.
8. The receiver integrated circuit of claim 1 , embodied as a memory integrated circuit.
9. A receiver integrated circuit, comprising:
data receivers to receive data over respective transmission lines of a digital bus in a signaling system from a transmitter integrated circuit of the signaling system, the data receivers including at least one circuit to compare;
wherein, in a test mode, a first one of the data receivers is to sample its respective transmission line in the signaling system as a victim line in the presence of cross talk contributed to the victim line from a same test signal transmitted over others of the other transmission lines as aggressor lines; and
wherein the at least one circuit to compare is to generate an output responsive to the sampling by the first one of the data receivers of its respective the transmission line in the signaling system to measure a performance characteristic of the signaling system as a function of the cross talk.
10. The receiver integrated circuit of claim 9 , wherein the at least one circuit to compare comprises a circuit to compare for each of the data receivers, wherein during the test mode each of the data receivers including the first one is to sample, at respective times relative to the other data receivers, its respective transmission line in the signaling system as a victim line in the presence of cross talk contributed to the victim line from a test signal transmitted over others of the other transmission lines as aggressor lines, and wherein the circuit to compare for each of the receivers is to generate a corresponding output responsive to sampling by the corresponding receiver of its respective transmission line to measure a performance characteristic of the signaling system as a function of the cross talk.
11. The receiver integrated circuit of claim 9 , wherein the circuit to compare further comprises circuitry to provide a multiplied clock for sampling of the victim line during the test mode so as to capture samples at a rate that is faster than a rate at which data is transmitted on the respective transmission line.
12. The receiver integrated circuit of claim 9 , wherein transmitters for at least two of the aggressor lines are to transmit in parallel the same test signal to the receiver integrated circuit and a transmitter for the victim line is to remain inactive while the first one of the data receivers samples its respective transmission line.
13. The receiver integrated circuit of claim 9 , wherein during the test mode, a transmitter for the victim line is to transmit a test signal while the first one of the data receivers samples its respective transmission line to measure a performance characteristic of the signaling system dependent on reflection interference on the victim line.
14. The receiver integrated circuit of claim 13 , where the same test signal is concurrent for each of at least two of the other transmission lines as aggressor lines.
15. The receiver integrated circuit of claim 9 , wherein the same test signal transmitted to the receiver integrated circuit over the others of the transmission lines is a single unit pulse, and wherein the receiver integrated circuit is to capture multiple samples of the victim line to measure crosstalk from the aggressor lines generated as a result of the single unit pulse.
16. The receiver integrated circuit of claim 9 , embodied as a memory integrated circuit.
17. A method of evaluating performance of a receiver integrated circuit in a signaling system, the method comprising:
using data receivers to receive data over respective transmission lines of a digital bus of the signaling system from a transmitter integrated circuit of the signaling system, the data receivers including at least one circuit to compare;
in a test mode, using a first one of the data receivers to sample its respective transmission line in the signaling system as a victim line in the presence of cross talk contributed to the victim line from a test signal transmitted over one or more others of the other transmission lines as aggressor lines, and using at least one circuit to compare is to generate an output responsive to the sampling by the first one of the data receivers of its respective transmission line to measure a performance characteristic of the signaling system as a function of the cross talk; and
evaluating performance of the receiver integrated circuit in dependence on the performance characteristic.
18. The method of claim 17 , wherein evaluating performance comprises measuring a worst case data eye margin, and evaluating performance in dependence on the worst case data eye margin.
19. The method of claim 18 , wherein evaluating performance comprises identifying at least one worst case bit pattern, and identifying the worst case data eye margin in dependence on the at least one worst case bit pattern.
20. The method of claim 17 , wherein the method further comprises during the test mode sequentially using each of the data receivers including the first one to sample its respective transmission line as a victim line in the presence of cross talk contributed to the victim line from a test signal transmitted over others of the other transmission lines as aggressor lines, and generating for each of the receivers a corresponding output responsive to sampling by the corresponding receiver of its respective transmission line to measure a performance characteristic of the signaling system as a function of the cross talk.
21. The method of claim 17 , wherein transmitters for at least two of the aggressor lines are to transmit in parallel a same test signal to the receiver integrated circuit and a transmitter for the victim line is to remain inactive while the first one of the data receivers samples its respective transmission line.