Conductive layers for hafnium silicon oxynitride films
Electronic apparatus and methods of forming the electronic apparatus include a HfSiON film on a substrate for use in a variety of electronic systems. The HfSiON film may be structured as one or more monolayers. The HfSiON film may be formed by atomic layer deposition. Electrodes to a dielectric containing a HfSiON may be structured as one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum. The titanium nitride and the tantalum may be formed by atomic layer deposition.
1. A method comprising:
forming a first nanolaminate on a substrate, the nanolaminate containing a first plurality of different insulating materials including a first layer of hafnium silicon oxynitride (Hf x Si y O z N r with x>0, y>0, z>0, and r>0), the first layer of hafnium silicon oxynitride formed using a self-limiting monolayer or partial monolayer sequencing process;
forming a layer of titanium nitride by the self-limiting monolayer or partial monolayer sequencing process on the first layer of hafnium silicon oxynitride;
forming a second nanolaminate on the substrate, the second nanolaminate containing a second plurality of different insulating materials including a second layer of hafnium silicon oxynitride (Wf k Si l O m N n with k>0, l>0, m>0, and n>0), the second layer of hafnium silicon oxynitride formed on the substrate using the self-limiting monolayer or partial monolayer sequencing process, the second layer of hafnium silicon oxynitride processed such that the second layer of hafnium silicon oxynitride is separate from the first layer of hafnium silicon oxynitride; and
forming a layer of tantalum by the self-limiting monolayer or partial monolayer sequencing process on the second layer of hafnium silicon oxynitride.
2. The method of claim 1 , wherein the method includes forming the titanium nitride as a gate and the first layer of hafnium silicon oxynitride as a gate insulator in a NMOS transistor.
3. The method of claim 2 , wherein forming the titanium nitride as a gate and the first layer of hafnium silicon oxynitride as a gate insulator in a NMOS transistor includes forming the titanium nitride and the first layer of hafnium silicon oxynitride such that the NMOS transistor has a threshold voltage of ranging from 0.2 to 0.3 Volts.
4. The method of claim 1 , wherein the method includes forming the tantalum as a gate and the second layer of hafnium silicon oxynitride as a gate insulator in a PMOS transistor.
5. The method of claim 1 , wherein forming the first layer of hafnium silicon oxynitride includes:
forming alternating layers of hafnium oxide and silicon nitride; and
annealing the alternating layers of hafnium oxide and silicon nitride to convert the layers of hafnium oxide and silicon nitride to the first layer of hafnium silicon oxynitride.
6. The method of claim 1 , wherein the method includes forming the first layer of hafnium silicon oxynitride or the second layer of hafnium silicon oxynitride as a capacitor dielectric in a capacitor.
7. The method of claim 1 , wherein the method includes forming the first layer of hafnium silicon oxynitride or the second layer of hafnium silicon oxynitride as a capacitor dielectric in a capacitor of a dynamic random access memory.
8. The method of claim 1 , wherein the method includes forming the first layer of hafnium silicon oxynitride or the second layer of hafnium silicon oxynitride as a capacitor dielectric in a capacitor of an analog integrated circuit.
9. The method of claim 1 , wherein the method includes forming the first layer of hafnium silicon oxynitride or the second layer of hafnium silicon oxynitride as a capacitor dielectric in a capacitor of a radio frequency integrated circuit.
10. The method of claim 1 , wherein the method includes forming the first layer of hafnium silicon oxynitride or the second layer of hafnium silicon oxynitride as a capacitor dielectric in a capacitor of a mixed signal circuit.
11. The method of claim 1 , wherein the method includes forming the first layer of hafnium silicon oxynitride or the second layer of hafnium silicon oxynitride as a tunnel gate insulator in a flash memory.
12. The method of claim 1 , wherein the method includes forming the first layer of hafnium silicon oxynitride or the second layer of hafnium silicon oxynitride as an inter-gate insulator in a flash memory.
13. The method of claim 1 , wherein the method includes forming the first layer of hafnium silicon oxynitride or the second layer of hafnium silicon oxynitride as a dielectric layer of a nano laminate in a NROM flash memory.
14. A method comprising:
forming a first nanolaminate disposed in an integrated circuit on a substrate, the nanolaminate containing a first plurality of different insulating materials including a first layer of hafnium silicon oxynitride (Hf x Si y O z N r with x>0, v>0, z>0, and r>0), the layer of hafnium silicon oxynitride formed using atomic layer deposition;
forming a titanium nitride layer by atomic layer deposition on the first layer of hafnium silicon oxynitride;
forming a second nanolaminate, the second nanolaminate containing a second plurality of different insulating materials including a second layer of hafnium silicon oxynitride (Hf k Si l O m N n with k>0, l>0, m>0, and n>0) using atomic layer deposition, the second nanolaminate disposed in the integrated circuit, the second layer of hafnium silicon oxynitride processed such that the second layer of hafnium silicon oxynitride is separate from the first layer of hafnium silicon oxynitride; and
forming a tantalum layer by atomic layer deposition on the second layer of hafnium silicon oxynitride.
15. The method of claim 14 , wherein the method includes forming the titanium nitride layer as a gate and the first layer of hafnium silicon oxynitride as a gate insulator in a NMOS transistor.
16. The method of claim 15 , wherein forming titanium nitride as a gate and the first layer of hafnium silicon oxynitride as a gate insulator in a NMOS transistor includes forming the titanium nitride and the layer of hafnium silicon oxynitride such that the NMOS transistor has a threshold voltage of ranging from 0.2 to 0.3 Volts.
17. The method of claim 14 , wherein the method includes forming tantalum as a gate and the second layer of hafnium silicon oxynitride as a gate insulator in a PMOS transistor.
18. The method of claim 14 , wherein the method includes forming the titanium nitride layer as a gate and the first layer of hafnium silicon oxynitride as a gate insulator in a NMOS transistor and forming the tantalum as a gate and the second layer of hafnium silicon oxynitride as a gate insulator in a PMOS transistor such that the NMOS transistor and the PMOS transistor have substantially symmetrical threshold voltages.
19. The method of claim 14 , wherein the method includes forming the first and second layers of hafnium silicon oxynitride as gate insulators in a CMOS structure.
20. The method of claim 19 , wherein the method includes forming the CMOS structure as a silicon-based CMOS structure.
21. The method of claim 14 , wherein forming a first layer of hafnium silicon oxynitride includes:
forming alternating layers of hafnium oxide and silicon nitride; and
annealing the alternating layers of hafnium oxide and silicon nitride to form hafnium silicon oxynitride.
22. The method of claim 14 , wherein forming a second layer of hafnium silicon oxynitride using atomic layer deposition includes using a silicon chloride precursor in the atomic layer deposition.
23. The method of claim 14 , wherein forming a second layer of hafnium silicon oxynitride using atomic layer deposition includes using NH 3 as a precursor in the atomic layer deposition.
24. The method of claim 14 , wherein forming a second layer of hafnium silicon oxynitride using atomic layer deposition includes using a hafnium halide precursor in the atomic layer deposition.
25. The method of claim 14 , wherein forming a second layer of hafnium silicon oxynitride using atomic layer deposition includes using a hafnium nitride precursor in the atomic layer deposition.
26. The method of claim 14 , wherein the method includes one of the first and second layers of hafnium silicon oxynitride as a capacitor dielectric in a capacitor and forming the other layer of hafnium silicon oxynitride as a gate insulator in a transistor.
27. The method of claim 14 , wherein the method includes forming a memory device.
28. The method of claim 27 , wherein forming a memory device includes forming the dielectric layer in a memory cell of a dynamic random access memory.
29. A method comprising:
providing a controller; and
coupling an integrated circuit to the controller, the integrated circuit formed by a method including:
forming a first nanolaminate on a substrate, the nanolaminate containing a first plurality of different insulating materials including a first layer of hafnium silicon oxynitride (Hf x Si y O z N r with x>0, v>0, z>0, and r>0), the first layer of hafnium silicon oxynitride formed using a self-limiting monolayer or partial monolayer sequencing process;
forming a layer of titanium nitride by the self-limiting monolayer or partial monolayer sequencing process on the first layer of hafnium silicon oxynitride;
forming a second nanolaminate on the substrate, the second nanolaminate containing a second plurality of different insulating materials including a second layer of hafnium silicon oxynitride (Hf k Si l O m N n with k>0, l>0, m>0, and n>0), the second layer of hafnium silicon oxynitride formed using the self-limiting monolayer or partial monolayer sequencing process, the second layer of hafnium silicon oxynitride processed such that the second layer of hafnium silicon oxynitride is separate from the first layer of hafnium silicon oxynitride; and
forming a layer of tantalum by the self-limiting monolayer or partial monolayer sequencing process on the second layer of hafnium silicon oxynitride.
30. The method of claim 29 , wherein the method includes the forming titanium nitride as a gate and the first layer of hafnium silicon oxynitride as a gate insulator in a NMOS transistor.
31. The method of claim 30 , wherein forming the titanium nitride as a gate and the first layer of hafnium silicon oxynitride as a gate insulator in a NMOS transistor includes forming the titanium nitride and the first layer of hafnium silicon oxynitride such that the NMOS transistor has a threshold voltage of ranging from 0.2 to 0.3 Volts.
32. The method of claim 29 , wherein the method includes forming the tantalum as a gate and the second layer of hafnium silicon oxynitride as a gate insulator in a PMOS transistor.
33. The method of claim 29 , wherein the self-limiting monolayer or partial monolayer sequencing process includes atomic layer deposition.
34. The method of claim 29 , wherein the method includes forming the titanium nitride layer as a gate and the first layer of hafnium silicon oxynitride as a gate insulator in a NMOS transistor and forming the tantalum as a gate and the second layer of hafnium silicon oxynitride as a gate insulator in a PMOS transistor such that the NMOS transistor and the PMOS transistor have substantially symmetrical threshold voltages.
35. The method of claim 29 , wherein the method includes forming the first and second layers of hafnium silicon oxynitride as gate insulators in a CMOS structure.
36. The method of claim 35 , wherein the method includes forming the CMOS structure as a silicon-based CMOS structure.
37. The method of claim 33 , wherein the method includes one of the first or second layers of hafnium silicon oxynitride as a capacitor dielectric in a capacitor and forming the other layer of hafnium silicon oxynitride as a gate insulator in a transistor.
38. The method of claim 1 , wherein the method includes forming the titanium nitride layer as a gate and the first layer of hafnium silicon oxynitride as a gate insulator in a NMOS transistor and forming the tantalum as a gate and the second layer of hafnium silicon oxynitride as a gate insulator in a PMOS transistor such that the NMOS transistor and the PMOS transistor have substantially symmetrical threshold voltages.
39. A method comprising:
forming a first layer of hafnium silicon oxynitride (Hf x Si y O z N r with x>0, y>0, z>0, and r>0) on a substrate, the first layer of hafnium silicon oxynitride formed using a self-limiting monolayer or partial monolayer sequencing process;
forming a layer of titanium nitride by the self-limiting monolayer or partial monolayer sequencing process on the first layer of hafnium silicon oxynitride;
forming a second layer of hafnium silicon oxynitride (Hf k Si l O m N n with k>0, l>0, m>0, and n>0), the second layer of hafnium silicon oxynitride formed on the substrate using the self-limiting monolayer or partial monolayer sequencing process, the second layer of hafnium silicon oxynitride processed such that the second layer of hafnium silicon oxynitride is separate from the first layer of hafnium silicon oxynitride; and
forming a layer of tantalum by the self-limiting monolayer or partial monolayer sequencing process on the second layer of hafnium silicon oxynitride, wherein forming the first and/or second layer of hafnium silicon oxynitride includes:
forming alternating layers of hafnium oxide and silicon nitride using the self-limiting monolayer or partial monolayer sequencing process; and
annealing the alternating layers of hafnium oxide and silicon nitride to convert the layers of hafnium oxide and silicon nitride to the respective layer of hafnium silicon oxynitride.