Method and apparatus for testing a data processing system
View Patent ↗A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.
1. A method for testing at least one logic block of a processor, comprising:
during execution of a user application by the processor, the processor generating a stop and test indicator, in response to the generation of the stop and test indicator stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor; and
applying a test stimulus for testing the at least one logic block of the processor.
2. The method of claim 1 further comprising decoding a stop and test instruction by the processor to generate the stop and test indicator.
3. The method of claim 2 further comprising decoding the stop and test instruction to determine a scan chain configuration prior to applying the test stimulus.
4. The method of claim 1 , wherein applying the test stimulus further comprises shifting in the test stimulus into at least one scan chain for a plurality of clock cycles.
5. The method of claim 4 wherein the at least one scan chain corresponds to the at least one logic block of the processor.
6. The method of claim 4 further comprising resetting the at least one logic block of the processor before shifting in the test stimulus.
7. The method of claim 4 further comprising shifting out a first set of test results corresponding to a first check point out of the at least one scan chain and receiving the first set of test results into a signature analyzer to generate a first signature corresponding to the first set of test results, wherein the first checkpoint corresponds to a first plurality of clock cycles, and comparing the first signature to a first expected signature.
8. The method of claim 7 further comprising shifting out a second set of test results corresponding to a second check point out of the at least one scan chain and receiving the second set of test results into the signature analyzer to generate a second signature corresponding to the second set of test results, wherein the second checkpoint corresponds to a second plurality of clock cycles, and comparing the second signature to a second expected signature.
9. The method of claim 4 , wherein the at least one scan chain comprises at least a first memory element, a chain of memory elements, and a second memory element, wherein an output of the first memory element is connected to an input of the chain of memory elements and to an input of at least one logic gate, and an output of the at least one logic gate is connected to an input of the second memory element.
10. The method of claim 9 , wherein the at least one logic gate is at least one of an exclusive-OR gate or an exclusive-NOR gate.
11. The method of claim 1 further comprising operating the at least one logic block of the processor using the test stimulus.
12. The method of claim 1 further comprising in response to a receipt of an interrupt, executing the user application on the processor.
13. The method of claim 12 , wherein executing the user application includes executing the user application beginning at a restore vector.
14. The method of claim 13 , wherein executing the user application further comprises restoring the state of the at least one logic block of the processor, if the state of the at least one logic block of the processor was saved.
15. The method of claim 1 , wherein the plurality of clock cycles has at least one of a predetermined maximum value and a predetermined minimum value.
16. The method of claim 1 further comprising shifting out test results out of the at least one scan chain and receiving the test results into a signature analyzer to generate at least one signature corresponding to the test results.
17. The method of claim 16 further comprising comparing the at least one signature to a corresponding expected signature.
18. An apparatus for testing at least one logic block of a processor, comprising:
a test controller configured to, during execution of a user application by the processor, generate a stop and test indicator, in response to the generation of the stop and test indicator stop the execution of the user application and, if necessary, save a state of the at least one logic block of the processor;
at least one scan chain, wherein the test controller is further configured to input a test stimulus for testing the at least one logic block of the processor into the at least one scan chain for a plurality of clock cycles and output test results out of the at least one scan chain;
a pattern generator configured to generate the test stimulus; and
a signature analyzer configured to generate at least one signature corresponding to the output results and comparing the at least one signature to a corresponding expected signature.
19. The apparatus of claim 18 further comprising a test results register configured to store at least one value indicating test success or failure.
20. The apparatus of claim 19 , wherein the test results register is further configured to store a value quantifying the plurality of clock cycles.
21. The apparatus of claim 19 , wherein the test results register is further configured to store a value corresponding to a number of clock cycles for a last completed checkpoint.
22. The apparatus of claim 18 further comprising a test results register configured to store a plurality of values indicating test success or failure, wherein each one of the plurality of values corresponds to a checkpoint.
23. The apparatus of claim 18 , wherein the test controller is further configured to generate a forced error signal causing the at least one signature to not match the corresponding expected signature.
24. The apparatus of claim 23 , wherein the forced error signal causes a variation in an output of the pattern generator.
25. The apparatus of claim 18 further comprising setting registers of the at least one logic block of the processor to a predetermined value prior to the generation of the stop and test indicator.