Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data
View Patent ↗Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal, respectively. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. In a multi-level implementation, the received signal is sampled using a clock associated with each of the levels and the samples are latched using a vertical slicing technique to generate DFE data associated with each of said levels.
1. A method for generating one or more clock signals in a receiver employing decision-feedback equalization, comprising:
sampling a received signal using a data clock and a transition clock to generate a data sample signal and a transition sample signal;
obtaining a DFE correction for each of said data sample and transition sample signals to generate DFE detected data and DFE transition data; and
adjusting a phase of one or more of said data clock and said transition clock based said DFE detected data and said DFE transition data.
2. The method of claim 1 , wherein said DFE corrections are subtracted from said received signal in a feedback fashion.
3. The method of claim 1 , wherein said DFE corrections are selected using DFE logic from a plurality of precomputed values to generate said DFE detected data and said DFE transition data.
4. The method of claim 3 , wherein at least one of said DFE detected data and said DFE transition data are based on a prior decision.
5. The method of claim 1 , further comprising the step of applying an output of said phase detector to a clock and data recovery circuit that generates said data and transition clocks.
6. The method of claim 1 , wherein said phase detector is a bang-bang phase detector.
7. The method of claim 1 , wherein said phase detector is a multi-level oversampled phase detector.
8. The method of claim 7 , wherein said sampling step further comprises the step of sampling said received signal using a clock associated with each of said levels.
9. The method of claim 8 , further comprising the step of selecting from a plurality of precomputed values to generate DFE data associated with each of said levels.
10. The method of claim 7 , further comprising the step of latching said samples using a vertical slicing technique to generate DFE data associated with each of said levels.
11. A receiver employing decision-feedback equalization, comprising:
a plurality of switches to sampling a received signal using a data clock and a transition clock to generate a data sample signal and a transition sample signal;
at least one decision-feedback equalization (DFE) block for generating a DFE correction for each of said data sample and transition sample signals to generate DFE detected data and a DFE transition data; and
a phase detector for adjusting a phase of one or more of said data clock and said transition clock based said DFE detected data and said DFE transition data.
12. The receiver of claim 11 , wherein said DFE corrections are subtracted from said received signal in a feedback fashion.
13. The receiver of claim 11 , further comprising DFE logic for selecting said DFE corrections from a plurality of precomputed values to generate said DFE detected data and said DFE transition data.
14. The receiver of claim 13 , wherein at least one of said DFE detected data and said DFE transition data are based on a prior decision.
15. The receiver of claim 11 , wherein an output of said phase detector is applied to a clock and data recovery circuit that generates said data and transition clocks.
16. The receiver of claim 11 , wherein said phase detector is a bang-bang phase detector.
17. The receiver of claim 11 , wherein said phase detector is a multi-level oversampled phase detector.
18. The receiver of claim 17 , wherein said plurality of switches sample said received signal using a clock associated with each of said levels.
19. The receiver of claim 18 , further comprising DFE logic to generate DFE data associated with each of said levels from a plurality of precomputed values.
20. The receiver of claim 17 , further comprising a plurality of latches for latching said samples using a vertical slicing technique to generate DFE data associated with each of said levels.
21. A receiver employing decision-feedback equalization, comprising:
a plurality of switches to sampling a received signal using a data clock and a transition clock to generate a data sample signal and a transition sample signal;
at least one decision-feedback equalization (DFE) block for generating a plurality of precomputed DFE corrections for each of said data sample and transition sample signals;
DFE logic for selecting one of said precomputed DFE corrections to generate said DFE detected data and said DFE transition data; and
a phase detector for adjusting a phase of one or more of said data clock and said transition clock based said DFE detected data and said DFE transition data.
22. The receiver of claim 21 , wherein an output of said phase detector is applied to a clock and data recovery circuit that generates said data and transition clocks.