Process for manufacturing semiconductor integrated circuit device
View Patent ↗In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
1. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer including copper as its principal component over an insulating film over a first major surface of a wafer by electroplating, the insulating film having a wiring groove pattern;
(b) removing the metal layer outside the wiring groove pattern by a chemical mechanical polishing method so as to leave the metal layer in the wiring groove pattern, said removing being performed in a chemical mechanical polishing section of a single wafer processing apparatus;
(c) after step (b), transferring the wafer to a post cleaning section of the single wafer processing apparatus, while keeping a surface of the metal layer left in the wiring groove pattern of the first major surface of the wafer wet with moving water, wherein the moving water is a water shower;
(d) performing scrub or brush cleaning to the first major surface of the wafer with a liquid chemical or pure water in the post cleaning section; and
(e) after step (d), making the first major surface of the wafer dry,
wherein the single wafer processing apparatus has a light shielding structure keeping an illuminance of the post cleaning section and a portion between the chemical mechanical polishing section and the post cleaning section 100 lux or less, and
wherein the light shielding structure includes a light shielding sheet.
2. A process for manufacturing a semiconductor integrated circuit device according to claim 1 , wherein step (d) is performed prior to a substantial progress of corrosion of the surface of the metal layer left in the wiring groove pattern.
3. A process for manufacturing a semiconductor integrated circuit device according to claim 2 , wherein the surface of the metal layer left in the wiring groove pattern of the first major surface of the wafer is kept wet from the end of step (b) to the end of step (d).
4. A process for manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the metal layer left in the wiring groove pattern in step (b) constitutes a portion of a metal wiring of a dual damascene wiring.
5. A process for manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the surface of the metal layer left in the wiring groove of the first major surface of the wafer is kept wet from the end of step (b) to the end of step (d).
6. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer over an insulating film over a first major surface of a wafer by electroplating, the insulating film having first and second wiring groove patterns;
(b) removing the metal layer outside the first and second wiring groove patterns by a chemical mechanical polishing method so as to leave the metal layer in the first and second wiring groove patterns and thereby electrically dividing metal wiring members inside the first and second wiring groove patterns, said removing being performed in a chemical mechanical polishing section of a single wafer processing apparatus, wherein portions of the metal layer left inside the first and second wiring groove patterns in step (b) constitute portions of metal wiring members of a dual damascene wiring;
(c) after step (b), transferring the wafer to a post cleaning section of the single wafer processing apparatus, while keeping a surface of the metal layer left in the first and second wiring groove patterns of the first major surface of the wafer wet with moving water, wherein the moving water is a pure water shower;
(d) performing scrub or brush cleaning to the first major surface of the wafer with a liquid chemical or pure water in the post cleaning section, wherein step (d) is performed prior to a substantial progress of corrosion of the surface of the metal layer left in the first and second wiring groove patterns; and
(e) after step (d), making the first major surface of the wafer dry,
wherein the single wafer processing apparatus has a light shielding structure keeping an the post cleaning section and a portion between the chemical mechanical polishing section and the post cleaning section 100 lux or less, and
wherein the surface of the metal layer left in the first and second wiring groove patterns of the first major surface of the wafer is kept wet from the end of step (b) to the end of step (d).
7. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer including copper as its principal component over an insulating film over a first major surface of a wafer by electroplating, the insulating film having a wiring groove pattern;
(b) removing the metal layer outside the wiring groove pattern by a chemical mechanical polishing method so as to leave the metal layer in the wiring groove pattern, said removing being performed in a chemical mechanical polishing section of a single wafer processing apparatus, wherein the metal layer left in the wiring groove pattern in step (b) constitutes a portion of a metal wiring of a dual damascene wiring;
(c) after step (b), transferring the wafer to a post cleaning section of the single wafer processing apparatus, while keeping a surface of the metal layer left in the wiring groove pattern of the first major surface of the wafer wet with moving water, wherein the moving water is a water shower;
(d) performing scrub or brush cleaning to the first major surface of the wafer with a liquid chemical or pure water in the post cleaning section; and
(e) after step (d), making the first major surface of the wafer dry,
wherein the single wafer processing apparatus has a light shielding structure keeping an illuminance of the post cleaning section and a portion between the chemical mechanical polishing section and the post cleaning section 100 lux or less, and
wherein the light shielding structure includes a light shielding sheet.
8. A process for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) forming a metal layer including copper as its principal component over an insulating film over a first major surface of a wafer by electroplating, the insulating film having a wiring groove pattern;
(b) removing the metal layer outside the wiring groove pattern by a chemical mechanical polishing method so as to leave the metal layer in the wiring groove pattern, said removing being performed in a chemical mechanical polishing section of a single wafer processing apparatus, wherein the metal layer left in the wiring groove pattern in step (b) constitutes a portion of a metal wiring of a dual damascene wiring;
(c) after step (b), transferring the wafer to a post cleaning section of the single wafer processing apparatus, while keeping a surface of the metal layer left in the wiring groove pattern of the first major surface of the wafer wet with moving water, wherein the moving water is a pure water shower;
(d) performing scrub or brush cleaning to the first major surface of the wafer with a liquid chemical or pure water in the post cleaning section, wherein step (d) is performed prior to a substantial progress of corrosion of the surface of the metal layer left in the wiring groove pattern; and
(e) after step (d), making the first major surface of the wafer dry,
wherein the single wafer processing apparatus has a light shielding structure keeping an illuminance of the post cleaning section and a portion between the chemical mechanical polishing section and the post cleaning section 100 lux or less, and
wherein the surface of the metal layer left in the wiring groove pattern of the first major surface of the wafer is kept wet from the end of step (b) to the end of step (d).