Semiconductor device

1. A semiconductor device having a power supply protective element that is provided near a terminal and which connects the terminal to an another terminal, comprising:

a main wiring line connected with a power supply terminal or a ground terminal;

a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device;

an internal power supply protective element connected with the branch line; and

a branching portion at which the branch line branches off from the main wiring line;

wherein the branching portion is a contact at which the branch line branches off from the main wiring line and a line impedance per unit length is changed.

2. The semiconductor device according to claim 1 , wherein the branch line applies a power supply potential or a ground potential to the functional block.

3. The semiconductor device according to claim 1 , further comprising an input/output terminal protective element connected between a line connected with an input/output terminal and the main wiring line, and an internal power supply protective element connected with the branch line.

4. The semiconductor device according to claim 1 , wherein the branch line extends orthogonally to a direction in which the main wiring line extends.

5. A semiconductor device having a power supply protective element that is provided near a terminal and which connects the terminal to an another terminal, comprising:

a main wiring line connected with a power supply terminal or a ground terminal;

a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; and

an internal power supply protective element connected with the branch line,

wherein the branch line connected with the power supply terminal through the main wiring line is connected with a well region of the semiconductor device through a contact.

6. A semiconductor having a power supply protective element that is provided near a terminal and which connects the terminal to an another terminal, comprising:

a main wiring line connected with a power supply terminal or a ground terminal;

a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; and

an internal power supply protective element connected with the branch line,

wherein the branch line connected with the ground terminal through the main wiring line is connected with a substrate region of the semiconductor device through a contact.

7. A semiconductor device having a power supply protective element that is provided near a terminal and which connects the terminal to an another terminal, comprising:

a main wiring line connected with a power supply terminal or a ground terminal;

a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; and

an internal power supply protective element connected with the branch line,

wherein the internal power supply protective element and the functional block are formed in the same well or on the same substrate, and the semiconductor device further comprise a diffusion layer of the same conductivity type as the substrate applied with a substrate potential or applied with a well potential, between the internal power supply protective element and the functional block.

8. A method of designing a semiconductor device, comprising:

(a) calculating an amount of current (Iesd) that flows between a power supply terminal and a ground terminal upon electrostatic discharge, a wiring resistance value (Rv) of an expected discharge path on a power supply potential side, a wiring resistance value (Rs) of an expected discharge path on a ground potential side, a clamp voltage (Vc) under operation of a power supply protective element, an effective operation resistive component (Rc) of the power supply protective element, an amount of a surge current (Iesd 1 ) that flows into a terminal power supply protective element, and a breakdown voltage (Vx) of a gate insulating film of an internal circuit;

(b) determining whether or not a voltage difference between a reference voltage terminal and a surge-applied terminal exceeds a gate oxide film breakdown voltage due to a surge current resulting from ESD, based on the calculation result in (a);

(c) calculating, if it is determined in (b) that the voltage difference between the reference voltage terminal and the surge-applied terminal exceeds the gate oxide film breakdown voltage, a line resistance value (Rdv) of a predicted discharge path on the power supply potential side, a line resistance value (Rds) of a predicted discharge path on the ground potential side, an effective operation resistive component (Rdc) of the power supply protective element connected with at least one of a power supply branch line and a ground branch line, a clamp voltage (Vdc) under operation of the power supply protective element connected with at least one of a power supply branch line and a ground branch line, an amount of a surge current (Iesd 1 ) that flows into a terminal power supply protective element upon formation of the internal power supply protective element, and an amount of a surge current (Iesd 2 ) that flows into the internal power supply protective element; and

(d) forming the internal power supply protective element in a portion where the voltage difference between the reference voltage terminal and the surge-applied terminal does not exceed the gate oxide film breakdown voltage based on the calculation result in (c).

9. The method of designing a semiconductor device according to claim 8 , wherein if a relation represented by Expression 1:

Iesd ( Rv+Rs+Rc )+ Vc>Vx   Expression 1

is met, (b) the determining includes connecting at least one of the power supply branch line and the ground branch line with the internal power supply protective element.

10. The method of designing a semiconductor device according to claim 8 , wherein (d) the forming includes connecting at least one of the power supply branch line and the ground branch line with the internal power supply protective element that satisfies Expression 2:

Iesd 1( Rv+Rs+Rc )+ Vc<Iesd 2( Rdv+Rds+Rdc )+ Rdc<Vx   Expression 2.

11. The method of designing a semiconductor device according to claim 9 , wherein (b) the determining includes deciding that no internal power supply protective element is provided if the relation represented by Expression 1 is not met.