Manufacturing method of semiconductor device
View Patent ↗A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H 2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.
1. A manufacturing method of a semiconductor device comprising the steps of:
forming a low dielectric film including a bond of Si and C on a substrate;
forming a via hole or a wiring groove in said low dielectric film;
conducting a plasma treatment using He gas on an exposed surface of said low dielectric film including said via hole or wiring grove, while applying RF bias of 250 W to 400 W;
forming a barrier metal on said exposed surface of said via hole or wiring groove formed in said low dielectric film, said barrier metal being made of tantalum nitride (TaN) on a side of said low dielectric film and tantalum (Ta) on the other side; and
embedding a wiring material in said via hole or wiring groove, whose surfaces are covered by said barrier metal, formed in said low dielectric film.
2. A manufacturing method of a semiconductor device, comprising the steps of:
forming at least a first interlayer insulation film and a second interlayer insulation film sequentially on a substrate in which a wiring pattern has been formed;
forming a via hole penetrating through said first interlayer insulation film and said second interlayer insulation film using a first resist pattern formed on said second interlayer insulation film;
removing said first resist pattern and then forming a trench pattern through etching of said second interlayer insulation film using a second resist pattern formed on said second interlayer insulation film;
depositing a barrier metal on said second interlayer insulation film and on inner walls of said via hole and said trench pattern;
depositing a wiring material and then embedding said wiring material in interiors of said via hole and said trench pattern; and
removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, wherein:
at least one of said first interlayer insulation film and said second interlayer insulation film is a low dielectric film having a bond of Si and C; and
a plasma treatment is performed before said barrier metal is deposited, using He gas on an exposed surface of said low dielectric film including said via hole and said stretch pattern, while applying RF bias of 250 W to 400 W.
3. A manufacturing method of a semiconductor device, comprising the steps of:
depositing at least a first interlayer insulation film, a second interlayer insulation film, and a hard mask material on a substrate in which a wiring pattern has been formed;
forming a hard mask through etching of said hard mask material using a first resist pattern formed on said hard mask material;
forming a via hole penetrating through said first interlayer insulation film and said second interlayer insulation film using a second resist pattern formed on said hard mask;
removing said second resist pattern and then forming a trench pattern through etching of said second interlayer insulation film using said hard mask;
depositing a barrier metal on said second interlayer insulation film and on inner walls of said via hole and said trench pattern;
depositing a wiring material and then embedding said wiring material in interiors of said via hole and said trench pattern; and
removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, wherein:
at least one of said first interlayer insulation film, said second interlayer insulation film, and said hard mask is a low dielectric film having a bond of Si and C; and
a plasma treatment is performed before said barrier metal is deposited, using He gas on an exposed surface of said low dielectric film including said via hole and said stretch pattern, while applying RF bias of 250 W to 400 W.
4. A manufacturing method of a semiconductor device comprising the steps of:
forming a low dielectric film including a bond of Si and C on a substrate;
forming a via hole or a wiring groove in said low dielectric film;
conducting a plasma treatment using a mixed gas of He and H 2 on an exposed surface of said low dielectric film including said via hole or wiring groove;
forming a barrier metal on said exposed surface of said via hole or wiring groove formed in said low dielectric film, said barrier metal being made of tantalum nitride (TaN) on a side of said low dielectric film and tantalum (Ta) on the other side; and
embedding a wiring material in said via hole or wiring groove, whose surfaces are covered by said barrier metal, formed in said low dielectric film.
5. The manufacturing method of a semiconductor device as claimed in claim 4 , wherein the ratio of H 2 gas to said mixed gas is 1 to 10%.
6. A manufacturing method of a semiconductor device, comprising the steps of;
forming at least a first interlayer insulation film and a second interlayer insulation film sequentially on a substrate in which a wiring pattern has been formed;
forming a via hole penetrating through said first interlayer insulation film and said second interlayer insulation film using a first resist pattern formed on said second interlayer insulation film;
removing said first resist pattern and then forming a trench pattern through etching of said second interlayer insulation film using a second resist pattern formed on said second interlayer insulation film;
depositing a barrier metal on said second interlayer insulation film and on inner walls of said via hole and said trench pattern, said barrier metal being made of tantalum nitride (TaN) on said via hole and said trench pattern;
depositing a wiring material and then embedding said wiring material in interiors of said via hole and said trench pattern; and
removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, wherein:
at least one of said first interlayer insulation film and said second interlayer insulation film is a low dielectric film having a bond of Si and C: and
a plasma treatment is performed before said barrier metal is deposited, using a mixed gas of He and H 2 on an exposed surface of said low dielectric film including said via hole and said trench pattern.
7. The manufacturing method of a semiconductor device as claimed in claim 5 , wherein the ratio of H 2 gas to said mixed gas is 1 to 10%.
8. A manufacturing method of a semiconductor device, comprising the steps of:
depositing at least a first interlayer insulation film, a second interlayer insulation film, and a hard mask material on a substrate in which a wiring pattern has been formed;
forming a hard mask through etching of said hard mask material using a first resist pattern formed on said hard mask material;
forming a via hole penetrating through said first interlayer insulation film and said second interlayer insulation film using a second resist pattern formed on said hard mask;
removing said second resist pattern and then forming a trench pattern through etching of said second interlayer insulation film using said hard mask;
depositing a barrier metal on said second interlayer insulation film and on inner walls of said via hole and said trench pattern, said barrier metal being made of tantalum nitride (TaN) on a side of said low dielectric film and tantalum (Ta) on the other side;
depositing a wiring material and then embedding said wiring material in interiors of said via hole and said trench pattern; and
removing extra portion of said wiring material and said barrier metal through CMP and surface is planarized, wherein:
at least one of said first interlayer insulation film, said second interlayer insulation film, and said hard mask is a low dielectric film having a bond of Si and C: and
a plasma treatment is performed before said barrier metal is deposited, using a mixed gas of He and H 2 on an exposed surface of said low dielectric film including said via hole and said trench pattern.
9. The manufacturing method of a semiconductor device as claimed in claim 7 , wherein the ratio of H 2 gas to said mixed gas is 1 to 10%.