Dynamic data restore in thyristor-based memory device

1. A semiconductor device comprising:

a memory cell comprising a thyristor disposed electrically in series with an access device;

a restore circuit operable to apply periodic pulses to the memory cell to maintain its data state; and

a bit line to electrically interface the thyristor via the access device;

wherein the thyristor comprises a base region and a capacitor electrode capacitively coupled to the base region;

the access device comprises a MOSFET having a gateable channel disposed electrically in series between the thyristor and the bit line, and a gate electrode operable under bias to influence the gateable channel; and

the restore circuit is adapted to apply the periodic pulses to at least one of the bit line, the capacitor electrode, and the gate electrode.

2. The semiconductor device of claim 1 , further comprising:

a plurality of said memory cells disposed in a plurality of rows and columns to an array;

wherein a given row of the array comprises a first wordline and a second wordline, the first wordline is coupled to the gate electrodes for the MOSFETs across the row and the second wordline is coupled to the capacitor electrodes for the thyristors across the row;

the MOSFETs are disposed electrically in series between the bit lines and thyristors of their associated column; and

the restore circuit is adapted to apply the periodic pulses to at least one of the first wordlines, the second wordlines and the bit lines.

3. The semiconductor device of claim 2 , wherein the restore circuit is adapted to provide a low level signal to at least one bit line of the plurality while the periodic pulses are applied to at least one of the first wordlines for the data maintenance.

4. The semiconductor device of claim 2 , further comprising a detect circuit to determine a condition of the semiconductor device; and

wherein the restore circuit is operable to adjust at least one of frequency, amplitude, and pulse duration of the periodic pulses dependent upon the condition determined by the detect circuit.

5. The semiconductor device of claim 4 , wherein the detect circuit comprises:

a dummy cell having a thyristor and a MOSFET disposed in serial relationship between first and second supply nodes; and

wherein the restore circuit is operable to adjust the frequency of the periodic pulses based on the level of a signal at an intermediate node of the dummy cell located between the thyristor and the MOSFET.

6. A thyristor-based semiconductor memory device comprising:

a plurality of memory cells disposed in an array of rows and columns;

a plurality of bit lines associated with the respective columns of the array;

at least one memory cell of the plurality comprising:

a thyristor;

a MOSFET comprising a gatable channel disposed serially between the thyristor and a given bit line of the plurality for the column associated with the memory cell; and

a capacitor electrode capacitively coupled to a base region of the thyristor;

a plurality of first wordlines associated with respective rows to the array, a given first wordline of the plurality to a given row coupled to the gates of the MOSFETs across said row;

a plurality of second wordlines associated with the respective rows to the array, a given second wordline of the plurality to a given row coupled to the capacitor electrodes to the thyristors across said row; and

a restore circuit to periodically pulse at least one of the first wordlines, the second wordlines, and the bit lines to maintain data per the bi-stable operability of the thyristor(s) of at least one of the memory cells of the array.

7. The device of claim 6 , wherein the restore circuit is operable during a given epoch of the periodic pulsing for the data maintenance to

provide a low level signal to the bit line(s) of the column(s) associated with the at least one memory cell; and

while providing the low level signal to the bit line(s) of the column(s) associated with the at least one memory cell, apply a pulse to at least one of the first wordline(s) and the second wordline(s) associated with the at least one memory cell.

8. The device of claim 7 , wherein the restore circuit is operable during said epoch of the periodic pulsing for the data maintenance to apply the pulse to the first wordline(s) associated with the row(s) for the at least one memory cell.

9. The device of claim 8 , wherein the restore circuit is operable during said epoch of the periodic pulsing for data maintenance to apply the pulse to a plurality of said first wordlines.

10. The device of claim 9 , wherein the restore circuit is further operable to discern a temperature and adjust at least one duty cycle of the periodic pulses dependent upon the temperature discerned.

11. A method of operating a thyristor-based semiconductor memory device having a thyristor disposed electrically in series with a MOSFET for a memory cell, said method comprising:

applying periodic pulses to the memory cell to maintain a bi-stable state of the thyristor within the memory cell.

12. The method of claim 11 , in which the memory cell is part of a plurality of memory cells that defines an array of rows and columns, and each memory cell of the array has such thyristor disposed electrically in series with such MOSFET and also a capacitor electrode capacitively coupled to a base region of the thyristor;

wherein the periodic pulses are applied to at least one wordline associated with respective at least one row of the array to enable the MOSFETs of the memory cells across said at least one row.

13. The method of claim 12 , in which the thyristor-based semiconductor memory device further comprises a plurality of bit lines associated with the respective columns of the array, and each bit line is coupled to the MOSFETs of the memory cells within their respective column, said method further comprising:

providing a low level signal to the at least one of the bit lines during at least a portion of time associated with the pulse width applied to the wordline.

14. The method of claim 13 , further comprising:

determining a standby mode of operation; and

conditioning when the low level signal is to be applied to the at least one of the bit lines and when the periodic pulses are to be applied to the wordlines dependent upon the standby mode being determined.

15. The method of claim 14 , further comprising:

discerning a temperature of the memory cell; and

adjusting the duty cycle of the periodic pulses dependent on the temperature discerned.

16. The method of claim 14 , further comprising:

discerning a temperature;

adjusting at least one of frequency, amplitude, and duration of the pulses associated with the periodic pulses dependent on the temperature discerned.

17. The method of claim 14 , further comprising:

discerning a voltage of an intermediate node of a dummy cell;

comparing the voltage discerned to a reference voltage; and

adjusting at least one of frequency, amplitude, and duration of the periodic pulses dependent upon the comparison.

18. The method of claim 17 , in which the dummy cell comprises a thyristor and a MOSFET disposed in serial arrangement between a first supply node and a second supply node; and

the discerning discerns the voltage signal at the intermediate node between the thyristor and the MOSFET.