IP Library Granted Patent US 7,323,744
Granted Patent B2
US 7,323,744 · App. 11/361,724 · Granted Jan 29, 2008

Semiconductor device and fabrication method therefor

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Quick Facts
Patent No.
US 7,323,744
App. No.
11/361,724
Granted
Jan 29, 2008
Kind
B2
Abstract

A semiconductor device includes an ONO film ( 17 ) formed on a semiconductor substrate ( 15 ), a first gate ( 14 ), the first gate ( 14 ) formed on the ONO film ( 17 ), a source ( 10 ) and a drain ( 12 ) provided at both sides of the first gate ( 14 ) to face each other, and a second gate ( 16 ), the second gate ( 16 ) being a side gate provided at a side of the first gate ( 14 ) other than the side where the source ( 10 ) and the drain ( 12 ) are provided. This makes it possible to provide the semiconductor device in which a desired circuit characteristic is obtainable in a non-destructive manner and in a non-volatile fashion while reducing the trial production times thereof for IC development.

Claims (20)

1. A semiconductor device comprising: an ONO film formed on a semiconductor substrate; a first gate, the first gate formed on the ONO film; a source provided in the semiconductor substrate at a first side of the first gate; a drain provided in the semiconductor substrate at a second side of the first gate opposite the first side, wherein the source and the drain face each other across the first gate to form a channel in the semiconductor substrate below the first gate; and a second gate, the second gate being a side gate provided at a third side of the first gate, wherein the third side is distinct from the first side where the source is provided and the second side where the drain is provided and is located above the semiconductor substrate and alongside the channel formed by the source and the drain in the semiconductor substrate.

2. The semiconductor device as claimed in claim 1 , further comprising an insulation film between the second gate and the channel.

3. The semiconductor device as claimed in claim 1 , wherein a transistor including the ONO film, the first gate, the source and the drain has an electrical characteristic changed in a non-volatile fashion in response to a voltage applied to the side second gate in a non-volatile fashion.

4. The semiconductor device as claimed in claim 3 , wherein a non-volatile change of the electrical characteristic of the transistor depends on a charge storage region formed in the ONO film.

5. The semiconductor device as claimed in claim 3 , wherein the electrical characteristic of the transistor includes at least one of a threshold voltage of the transistor and a drain current thereof.

6. The semiconductor device as claimed in claim 1 , wherein a charge is stored in a charge storage region formed in the ONO film.

7. A method of for fabricating a semiconductor device comprising: forming a transistor having a first gate and a second gate on a semiconductor substrate, the first gate formed over a channel in the semiconductor substrate between a source on a first side of the first gate and a drain on a second side of the first gate, wherein the second gate is formed between the source and the drain alongside the channel on a third side of the first gate, wherein the third side is different from the first and second sides of the first gate; and electrically changing and adjusting an electrical characteristic of the transistor in a non\- volatile fashion.

8. The method as claimed in claim 7 , wherein electrically adjusting the electrical characteristic of the transistor comprises:

checking the electrical characteristic of the transistor;

determining whether the electrical characteristic of the transistor is a desired characteristic; and

changing the electrical characteristic of the transistor in the non-volatile fashion if the electrical characteristic thereof is not the desired characteristic.

9. The method as claimed in claim 7 , wherein electrically adjusting the electrical characteristic comprises forming a charge storage region in an ONO film included in of the transistor.

10. The method as claimed in claim 7 , wherein the electrical characteristic of the transistor includes at least one of a threshold voltage of the transistor and a drain current thereof.

11. The method as claimed in claim 7 , wherein electrically changing and adjusting the electrical characteristic of the transistor comprises: electrically controlling a width of the channel of the transistor formed between the source and the drain; and programming or erasing a charge storage region in an ONO film included in the transistor.

12. The method as claimed in claim 11 , wherein electrically controlling the width of the channel comprises applying a voltage to the second gate.

13. A method of for controlling a semiconductor device comprising: checking an electrical characteristic of a transistor, the transistor having a first gate and a second gate, the first gate located over a channel formed between a source on a first side of the first gate and a drain on a second side of the first gate and the second gate is located alongside the channel between the source and the drain on a third side of the first gate different from the first and second sides thereof; and electrically changing adjusting the electrical characteristic of the transistor in a non-volatile fashion if the electrical characteristic of the transistor is not a desired characteristic.

14. The method as claimed in claim 13 , wherein electrically adjusting the electrical characteristic comprises forming a charge storage region in an ONO film included in the transistor.

15. The method as claimed in claim 13 , wherein the electrical characteristic of the transistor includes at least one of a threshold voltage of the transistor and a drain current thereof.

16. The method as claimed in claim 13 , wherein electrically adjusting the electrical characteristic of the transistor comprises: electrically controlling a width of the channel of the transistor; and programming or erasing a charge storage region in an ONO film included in the transistor.

17. The method as claimed in claim 16 , wherein electrically controlling the width of the channel of the transistor comprises applying a voltage to the second gate.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036037/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2006
From: HAYAKAWA, YUKIO
To: SPANSION LLC
Reel/Frame 017874/0306 →