Reducing effects of parasitic transistors in thyristor-based memory using local thinning or implanting
View Patent ↗Method and apparatus for an integrated circuit having memory including thyristor-based memory cells is described. A pair of the thyristor-based memory cells are commonly coupled via a bitline region, where a parasitic bipolar junction transistor is defined therebetween responsive to the bitline region being common. In another implementation, the pair of the thyristor-based memory cells are commonly coupled via the anode region, where a parasitic bipolar junction transistor is defined therebetween responsive to the anode region being common. The common bitline or anode region, respectively, has a locally thinned region to inhibit charge transfer between the pair via the parasitic bipolar junction transistor. Moreover, a method for forming a field-effect transistor on a silicon-on-insulator wafer is described, where charge transfer facilitated by a parasitic bipolar transistor is reduced responsive to an increase in dopants at least proximate to an insulator layer.
1. An integrated circuit having memory, comprising:
thyristor-based memory cells, each of the thyristor-based memory cells including a thyristor-based storage element and an access transistor, the thyristor-based storage element including an anode region and a cathode region in a substrate;
a first pair of the thyristor-based memory cells commonly coupled via a bitline region in the substrate associated with the access transistor;
the first pair of the thyristor-based memory cells defining a first parasitic bipolar junction transistor therebetween responsive to the bitline region being common; and
the bitline region having a first locally thinned region to inhibit charge transfer between the first pair of the thyristor-based memory cells via the first parasitic bipolar junction transistor;
wherein the first locally thinned region is approximately 50 to 80 percent in profile thickness of the bitline region prior to etching to form the first locally thinned region; and
wherein the bitline region is silicided in the first locally thinned region to provide a first salicide region disposed in the first locally thinned region.
2. The integrated circuit according to claim 1 , further comprising:
a second pair of the thyristor-based memory cells commonly coupled via the anode region;
the second pair of the thyristor-based memory cells defining a second parasitic bipolar junction transistor therebetween responsive to the anode region being common; and
the anode region having a second locally thinned region to inhibit charge transfer between the second pair via the second parasitic bipolar junction transistor.
3. The integrated circuit according to claim 2 , wherein the anode region is silicided in the second locally thinned region to provide a second salicide region disposed in the second locally thinned region.
4. The integrated circuit according to claim 3 , wherein:
the access transistor and the thyristor-based storage element are commonly coupled via the cathode region;
the access transistor and the thyristor-based storage element define a third parasitic bipolar junction transistor therebetween responsive to the cathode region being common; and
the cathode region has a third locally thinned region to inhibit charge transfer between the access transistor and the thyristor-based storage element via the third parasitic bipolar junction transistor.
5. The integrated circuit according to claim 4 , wherein the cathode region is silicided in the third locally thinned region to provide a third salicide region disposed in the third locally thinned region.
6. The integrated circuit according to claim 5 , wherein the bitline region is a source/drain region of the access transistor.
7. An integrated circuit having memory, comprising:
thyristor-based memory cells, each of the thyristor-based memory cells including a thyristor-based storage element, the thyristor-based storage element including an anode region and a cathode region in a substrate;
a pair of the thyristor-based memory cells commonly coupled via the anode region;
the pair of the thyristor-based memory cells defining a parasitic bipolar junction transistor therebetween responsive to the anode region being common; and
the anode region having a locally thinned region to inhibit charge transfer between the pair of the thyristor-based memory cells via the parasitic bipolar junction transistor;
wherein the locally thinned region is obtained by etching to reduce thickness of the anode region by approximately 20 to 50 percent; and
wherein the anode region is silicided in the locally thinned region to provide a salicide region disposed in the locally thinned region.
8. The integrated circuit according to claim 7 , wherein each of the thyristor-based memory cells includes an access transistor.
9. An integrated circuit having memory, comprising:
thyristor-based memory cells, each of the thyristor-based memory cells including a thyristor-based storage element, the thyristor-based storage element including an anode region and a cathode region in a substrate;
a parasitic bipolar junction transistor responsive to the cathode region being common with the thyristor-based storage element and another device; and
the cathode region having a locally thinned region to inhibit charge transfer between the pair of the thyristor-based memory cells via the parasitic bipolar junction transistor;
wherein the locally thinned region is obtained by etching to reduce thickness of the cathode region by approximately 20 to 50 percent; and
wherein the cathode region is silicided in the locally thinned region to provide a salicide region disposed in the locally thinned region.
10. The integrated circuit according to claim 9 , wherein the other device is an access transistor.