Biasing scheme for low supply headroom applications
View Patent ↗Methods and apparatus for improving the current matching within current mirror circuits in applications such as low voltage integrated circuits. Embodiments of the present invention attempt to maintain the proper current ratio between reference and output supplies by adjusting the reference output of the current mirror. An existing reference voltage on the output side of the mirror can be used or a reference voltage can be created to be used for the voltage regulation of the reference side of the current mirror.
1. A current mirror circuit, comprising:
a reference portion to provide a reference current, the reference portion including a first transistor, a second transistor, and a first resistor coupled between a gate of the first transistor and a drain of the second transistor; and
a load portion to provide a load current that is proportional to the reference current, the load portion including a third transistor having a gate that is coupled to the gate of the first transistor;
wherein a drain of the third transistor is coupled to a load circuit; and
wherein a resistance of the first resistor is based on a voltage of the load circuit.
2. The current mirror circuit of claim 1 , wherein a source of the first transistor and a source of the third transistor are coupled together.
3. The current mirror circuit of claim 1 , wherein the reference portion further includes a current source to provide a current to the first resistor; and wherein the resistance of the first resistor times the current is substantially equal to the voltage of the load circuit.
4. The current mirror circuit of claim 1 , wherein the resistor improves proportionality between the reference current and the load current.
5. The current mirror circuit of claim 1 , wherein the resistor improves a relationship between a drain-to-source voltage of the first transistor and a drain-to-source voltage of the third transistor.
6. The current mirror circuit of claim 1 , wherein a voltage at a gate of the second transistor is based on an input of the load circuit.
7. The current mirror circuit of claim 1 , wherein the load circuit is a differential load circuit including fourth and fifth transistors, and wherein a source of the fourth transistor and a source of the fifth transistor are coupled to a drain of the third transistor.
8. The current mirror circuit of claim 7 , wherein a voltage at a gate of the second transistor is based on an average voltage between a gate of the fourth transistor and a gate of the fifth transistor.
9. The current mirror circuit of claim 1 , wherein the reference portion further includes a second resistor coupled between a drain of the first transistor and a source of the second transistor.
10. The current mirror circuit of claim 9 , wherein a resistance of the second resistor is based on a resistance of the load circuit.
11. A current mirror circuit, comprising:
a reference portion to provide a reference current, the reference portion including a first transistor, a second transistor, and means for improving proportionality between the reference current and a load current that is proportional to the reference current, the means for improving coupled between a gate of the first transistor and a drain of the second transistor; and
a load portion to provide the load current, the load portion including a third transistor having a gate that is coupled to the gate of the first transistor;
wherein a drain of the third transistor is coupled to a load circuit; and
wherein a voltage across the means for improving is based on a voltage of the load circuit.
12. The current mirror circuit of claim 11 , wherein the means for improving includes a resistor having a resistance that is based on the voltage of the load circuit.
13. The current mirror circuit of claim 11 , wherein the means for improving includes a voltage source providing a voltage that is based on the voltage of the load circuit.
14. The current mirror circuit of claim 11 , wherein the load circuit is a differential load circuit including fourth and fifth transistors, and wherein a source of the fourth transistor and a source of the fifth transistor are coupled to a drain of the third transistor.
15. The current mirror circuit of claim 11 , wherein the reference portion further includes a resistor coupled between a drain of the first transistor and a source of the second transistor.
16. A current mirror circuit, comprising:
a reference portion to provide a reference current, the reference portion including a first transistor, a second transistor, and means for improving a relationship between a drain-to-source voltage of the first transistor and a drain-to-source voltage of a third transistor, the means for improving coupled between a gate of the first transistor and a drain of the second transistor; and
a load portion to provide a load current that is proportional to the reference current, the load portion including the third transistor, the third transistor having a gate that is coupled to the gate of the first transistor;
wherein a drain of the third transistor is coupled to a load circuit; and
wherein a voltage across the means for improving is based on a voltage of the load circuit.
17. The current mirror circuit of claim 16 , wherein the means for improving includes a first resistor having a resistance that is based on the voltage of the load circuit.
18. The current mirror circuit of claim 16 , wherein the means for improving includes a voltage source providing a voltage that is based on the voltage of the load circuit.
19. The current mirror circuit of claim 16 , wherein the load circuit is a differential load circuit including fourth and fifth transistors, and wherein a source of the fourth transistor and a source of the fifth transistor are coupled to a drain of the third transistor.
20. The current mirror circuit of claim 16 , wherein the reference portion further includes a resistor coupled between a drain of the first transistor and a source of the second transistor.