Integrated circuit testing module including data compression
View Patent ↗Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.
1. A system comprising:
one or more data receiving components configured to receive data from an integrated circuit under test at a first clock frequency;
a data compression component configured to compress the data received from the integrated circuit, to generate compressed data;
at least one input configured for receiving expected data or a multiplexing scheme for use by the data compression component; and
one or more data output components configured to convey the compressed data to automated testing equipment at a second clock frequency.
2. The system of claim 1 , wherein the integrated circuit is separable from the one or more data receiving components, and the second clock frequency is a lower frequency than the first clock frequency.
3. The system of claim 1 , wherein the data compression component is configured to compare the received data to an expected result and to communicate an output of this comparison to the automated testing equipment.
4. The system of claim 1 , wherein the data compression component is configured to compress the data received from the integrated circuit responsive to whether the address is even or odd.
5. The system of claim 1 , wherein the data compression component is configured to compress, the data received from the integrated circuit responsive to an invert odd or even bit mode.
6. The system of claim 1 , wherein the data compression component is configured to compress the data received from the integrated circuit in a serial compression stage.
7. The system of claim 6 , wherein the serial compression stage includes multiple comparisons of the data received from the integrated circuit to an expected data value.
8. The system of claim 1 , wherein the data compression component is configured to compress the data received from the integrated circuit in a parallel compression stage.
9. The system of claim 1 , wherein the data compression component is configured to compress the data received from the integrated circuit in both a serial compression stage and a parallel compression stage.
10. The system of claim 1 , wherein the data compression component is configured to compress the data received from the integrated circuit by a ratio of 4-to-1 or greater.
11. The system of claim 1 , wherein the one or more data receiving components and the one or more data output components are included in a test module, the test module being one of a plurality of test modules included in a test array configured for testing a plurality of integrated circuits.
12. The system of claim 11 , wherein the test array includes a memory configured to store the expected data, the memory being shared by the plurality of test modules.
13. The system of claim 1 , further comprising the automatic testing equipment configured for testing the integrated circuit and coupled to the one or more data output components.
14. A system comprising:
one or more data receiving components configured to receive data from an integrated circuit under test;
a data compression component configured to compress the data received from the integrated circuit to generate compressed data, the compression being responsive to an address within the integrated circuit from which the data was received;
at least one input configured for receiving expected data or a multiplexing scheme for use by the data compression component; and
one or more data output components configured to convey the compressed data to automated testing equipment.
15. The system of claim 14 , wherein the compression is further responsive to a mode in which odd bits or even bits are inverted.
16. The system of claim 14 , further including a command pin configured to receive a command on a first clock cycle and to receive part of the expected data on a second clock cycle.
17. The system of claim 14 , further including two or more pins configured for receiving the expected data.
18. The system of claim 14 , wherein the compression is further responsive to expected data received from the automated testing equipment.
19. A method comprising:
attaching an integrated circuit to be tested to a test module;
receiving data from the integrated circuit;
compressing the received data responsive to expected data, to generate compressed data; and
providing the compressed data to automated testing equipment.
20. The method of claim 19 , wherein the data is received from the integrated circuit at a first clock frequency and provided to the automated testing equipment at a second clock frequency.
21. The method of claim 19 , wherein compressing the received data is further responsive to an address within the integrated circuit from which the received data was received.
22. The method of claim 19 , wherein compressing the received data is further responsive to a mode in which even or odd bits are inverted.
23. The method of claim 19 , wherein compressing the received data is performed in both serial and parallel stages.
24. The method of claim 19 , wherein compressing the received data is performed responsive to a parallel compression multiplexing scheme.