Integrated circuit testing module including address generator
View Patent ↗Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.
1. A system for testing an integrated circuit using automated testing equipment comprising:
one or more input interfaces configured to receive test address data from the automated testing equipment at a first clock frequency;
an address generator configured to use the test address data to generate a plurality of addresses in the integrated circuit to be tested; and
one or more output interfaces configured to convey the plurality of addresses to the integrated circuit at a second clock frequency.
2. The system of claim 1 , wherein the address generator includes a column address generator configured to use the test address data to generate a plurality of column addresses and a row address generator configured to use the test address data generate a plurality of row addresses responsive to.
3. The system of claim 2 , wherein the column address generator is configured to generate column addresses independently from the row address generator.
4. The system of claim 1 , wherein the test address data includes a row counter value configured for generating row addresses.
5. The system of claim 1 , wherein the address generator includes a column address generator configured to generate at least two column addresses for each test column address represented by the test address data.
6. The system of claim 1 , wherein the address generator is configured to generate 4 or more addresses for each test address represented by the test address data.
7. The system of claim 1 , wherein the address generator is configured to use each test address represented by the test address data to generate a block of addresses.
8. The system of claim 1 , wherein the address generator is controllable to generate the plurality of row addresses in ascending or descending order.
9. The system of claim 1 , wherein the plurality of addresses are configured for reading data from the integrated circuit.