IP Library Granted Patent US 7,233,372
Granted Patent B2
US 7,233,372 · App. 11/373,285 · Granted Jun 19, 2007

Electro-optical device with a gap of the light shielding layer being in a non-overlapping condition with the drain and the source in plan view

Assignee: Seiko Epson Corporation
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Quick Facts
Patent No.
US 7,233,372
App. No.
11/373,285
Granted
Jun 19, 2007
Kind
B2
Abstract

An electro-optical device includes a display electrode disposed in an image display region of a TFT array substrate, a pattern portion including at least one of wiring and a circuit element connected to the display electrode directly or through a pixel switching element and provided in a frame region, which defines the periphery of the image display region, and a lower shielding film for covering the TFT array substrate side of at least a portion of the pattern portion. Therefore, in the electro-optical device such as a liquid crystal device, a light-dark pattern due to the wiring and the circuit element provided in the frame region can be prevented from being projected near the edge of a display image.

Claims (18)

1. An electro-optical device, comprising:

a light exit substrate;

a counter substrate opposing the light exit substrate;

a frame-shaped light shielding layer disposed over the counter substrate and defining an image display region;

a display electrode disposed over the light exit substrate within the image display region;

a pattern portion disposed over the light exit substrate at a position overlapping with the frame-shaped light shielding layer and within the image display region in plan view, the pattern portion being coupled to the display electrode and including a wiring and a transistor, the transistor including a source and a drain;

a lower light shielding layer outside the image display region and in overlap with the frame-shaped light shielding layer in plan view, the lower light shielding layer covering the pattern portion from a light exit side of the light exit substrate, the lower light shielding layer including a drain section confronting the drain of the transistor and a source section confronting the source of the transistor, the drain section and the source section of the lower light shielding layer being island shaped and separated from each other by a gap so that the drain section and the source section are isolated from each other by the gap, the gap being in a non-overlapping condition with the drain and the source in plan view.

2. An electro-optical device according to claim 1 , wherein the lower light shielding layer is formed over a flat surface of the light exit substrate either directly or via a flat underlying insulating film.

3. An electro-optical device according to claim 1 , further comprising:

a pixel switching transistor for switching on and off application of voltage to the display electrode; and

another lower light shielding layer disposed below at least the channel region of the pixel switching transistor, the lower light shielding layer and the other lower light shielding layer being formed from the same layer.

4. An electro-optical device according to claim 1 , wherein the lower light shielding layer is formed from a light-absorbing material.

5. An electro-optical device according to claim 4 , wherein the light-absorbing material is at least one of polysilicon and a metal film with a high melting point.

6. An electro-optical device according to claim 1 , wherein the lower light shielding layer is formed from an electrically conductive material.

7. An electro-optical device according to claim 1 , wherein the lower light shielding layer is applied at least locally with a fixed potential.

8. An electro-optical device according to claim 1 , the transistor further including a gate electrode, the slit overlapping the gate electrode of the transistor in plan view.

9. An electro-optical device according to claim 1 , the transistor further including a channel, the gap overlapping the channel of the transistor in plan view.

10. An electro-optical device according to claim 1 , the transistor further including a P-channel region and an N-channel region electrically connected together through the drain, the lower light shielding layer extending continuously under the entire drain.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2018
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 046551/0423 →
Priority Claims (2)
JP 2001-309103 · Oct 4, 2001 · national
JP 2002-264521 · Sep 10, 2002 · national
Continuity (2)
Continuation 1025939000 · Sep 30, 2002
Related Publication 20060152665A1 · Jul 13, 2006