Pattern forming method, semiconductor device manufacturing method and phase shift photomask having dummy gate patterns

1. A method for forming a plurality of gate patterns in parallel with each other on a photoresist layer within one circuit block, said method comprising:

forming at least one dummy gate pattern in parallel with said gate patterns when a pitch between said gate patterns is larger than a predetermined maximum pitch, so that pitches between said gate patterns including said dummy gate pattern are smaller than said predetermined maximum pitch, and are greater than a minimum pitch, which is a minimum distance between said gate patterns; and

after forming at least one dummy gate pattern and said gate patterns on said photoresist layer, performing a first photolithography process upon said photoresist layer by using a phase shift photomask having first and second openings whose difference in phase is π, said first and second openings alternating between said gate patterns including said dummy gate pattern to form phase edges therein.

2. The method as set forth in claim 1 , further comprising forming extension gate patterns on both ends of said gate patterns and said dummy gate pattern reaching an edge of said circuit block.

3. The method as set forth in claim 2 , further comprising performing a second photolithography process upon said photoresist layer by using a trim photomask having trim openings corresponding to said dummy gate pattern and said extension gate patterns to remove a portion of said photoresist layer corresponding to said dummy gate pattern and said extension gate patterns, after said first photolithography process is performed.

4. The method as set forth in claim 1 , further comprising performing a second photolithography process upon said photoresist layer by using a trim photomask having at least one trim opening corresponding to said dummy gate pattern to remove a portion of said photoresist layer corresponding to said dummy gate pattern, after said first photolithography process is performed.

5. The method as set forth in claim 1 , wherein a ratio of said maximum pitch to said minimum pitch is in a range from 1.3 to 1.7.

6. The method as set forth in claim 1 , wherein a ratio of said maximum pitch to said minimum pitch is in a range from 1.3 to 1.4.

7. The method as set forth in claim 1 , wherein a distance between each of gate patterns and each of dummy gate patterns is not constant.

8. The method as set forth in claim 1 , wherein said dummy gate pattern is formed only between two adjacent gate patterns.

9. A method for manufacturing a semiconductor device having a plurality of gate patterns in parallel with each other within one circuit block, said method comprising:

forming at least one dummy gate pattern in parallel with said gate patterns when a pitch between said gate patterns is larger than a predetermined maximum pitch, so that pitches between said gate patterns including said dummy gate pattern are smaller than said predetermined maximum pitch, and are greater than a minimum pitch, which is a minimum distance between said gate patterns;

after forming at least one dummy gate pattern and said gate patterns on said photoresist layer, performing a first photolithography process upon a photoresist layer within said circuit block by using a phase shift photomask having first and second openings whose difference in phase is π, said first and second openings alternating between said gate patterns including said dummy gate pattern to form phase edges therein;

performing a second photolithography process upon said photoresist layer by using a trim photomask having at least one trim opening corresponding to said dummy gate pattern to remove a portion of said photoresist layer corresponding to said dummy gate pattern, after said first photolithography process is performed; and

performing an etching process upon a conductive layer by using said photoresist layer subjected to said first and second photolithography processes as a mask.

10. The method as set forth in claim 9 , further comprising forming extension gate patterns on both ends of said gate patterns and said dummy gate pattern reaching an edge of said circuit block,

said trim photomask further having trim openings corresponding to said extension gate patterns.

11. The method as set forth in claim 9 , wherein a ratio of said maximum pitch to said minimum pitch is in a range from 1.3 to 1.4.

12. The method as set forth in claim 9 , wherein said dummy gate pattern is formed only between two adjacent gate patterns.

13. A method for manufacturing a semiconductor device having a plurality of gate patterns in parallel with each other within one circuit block, said method comprising:

forming at least one dummy gate pattern in parallel with said gate patterns when a pitch between said gate patterns is larger than a predetermined maximum pitch, so that pitches between said gate patterns including said dummy gate pattern are smaller than said predetermined maximum pitch, and are greater than a minimum pitch, which is a minimum distance between said gate patterns;

after forming at least one dummy gate pattern and said gate patterns on said photoresist layer, performing a first photolithography process upon a first photoresist layer within said circuit block by using a phase shift photomask having first and second openings whose difference in phase is π, said first and second openings alternating between said gate patterns including said dummy gate pattern to form phase edges therein;

performing a first etching process upon a conductive layer by using said first photoresist layer subjected to said first photolithography process as a mask;

removing said first photoresist layer and coating a second photoresist layer on said conductive layer after said first etching process is performed;

performing a second photolithography process upon said second photoresist layer by using a trim photomask having at least one trim opening corresponding to said dummy gate pattern to remove a portion of said photoresist layer corresponding to said dummy gate pattern; and

performing a second etching process upon said conductive layer by using said second photoresist layer subjected to said second photolithography process as a mask.

14. The method as set forth in claim 13 , further comprising forming extension gate patterns on both ends of said gate patterns and said dummy gate pattern reaching an edge of said circuit block,

said trim photomask further having trim openings corresponding to said extension gate patterns.

15. The method as set forth in claim 13 , wherein a distance between each of gate patterns and each of dummy gate patterns is not constant.

16. The method as set forth in claim 13 , wherein said dummy gate pattern is formed only between two adjacent gate patterns.