Chipset-independent method for locally and remotely updating and configuring system BIOS

1. A method for updating a non-volatile memory (NVM) included in an information handling system (IHS), the method comprising:

verifying a plurality of conditions permitting the updating of the NVM from a memory of the IHS;

preserving contents of the memory;

updating the NVM from the memory;

resetting the IHS in response to the updating by enabling a cold reboot; and

wherein verifying the plurality of conditions includes:

verifying a warm report status of the IHS;

verifying an update request bit set in another non-volatile memory (ANVM) of the IHS, the update request bit being indicative of a pending request to update the NVM from the memory; and

verifying a checksum error status of the ANVM.

2. The method of claim 1 , wherein the verifying of the warm reboot status is performed by:

reading a predefined location in the memory; and

verifying a match between contents stored at the predefined location and predefined data.

3. A method for updating a non-volatile memory (NVM) included in an information handling system (IHS), the method comprising:

verifying a plurality of conditions permitting the updating of the NVM from a memory of the IHS;

preserving contents of the memory;

updating the NVM from the memory;

resetting the IHS in response to the updating by enabling a cod reboot;

providing a user interface, wherein the user interface is provided prior to the updating; and

providing an output via the user interface, the output being indicative of a completion status of the updating.

4. The method of claim 3 , wherein the providing of the user interface includes:

enabling a display device; and

enabling a video interrupt.

5. A method for updating a non-volatile memory (NVM) included in an information handling system (IHS), the method comprising:

verifying a plurality of conditions permitting the updating of the NVM from a memory of the IHS;

preserving contents of the memory;

updating the NVM from the memory;

resetting the IHS in response to the updating by enabling a cold reboot; and

initializing interrupts capable of interrupting the updating;

disabling the interrupts to prevent interruption of the updating; and

disabling a bus master capable of changing the contents of the memory.

6. The method of claim 1 , wherein the updating of the NVM is independent of a chipset included in the IHS.

7. The method of claim 1 further comprising:

resetting a processor of the IHS, wherein the resetting of the processor causes the verifying of the plurality of conditions.

8. A method for updating a non-volatile memory (NVM) included in an information handling system (IHS), the method comprising:

verifying a plurality of conditions permitting the updating of the NVM from a memory of the IHS;

preserving contents of the memory;

updating the NVM from the memory; and

resetting the IHS in response to the updating by enabling a code reboot;

wherein the application program included in the IHS is executable for:

providing an updated image for the NVM;

storing the updated image in the memory; and

resetting a process of the ISH to initiate the updating of the NVM; and

wherein the updated image includes updated configuration of the IHS.

9. The method of claim 8 , wherein the updating of the NVM includes:

validating integrity of the memory;

uncompressing the updated image in the memory;

storing the updated image in the NVM;

setting a return code for the application program;

providing a completion status output; and

resetting at least one of the plurality of conditions.

10. The method of claim 1 , wherein the cold reboot of the IHS enables updates made to the NVM to take effect.

11. An information handling system (IHS) comprising:

a processor;

a bus coupled to the processor;

a memory coupled to the bus;

an NVM coupled to the bus; and

a basic input output system (BIOS) capable of updating the NVM, wherein the BIOS includes instructions for:

verifying a plurality of conditions permitting the updating of the NVM from the memory;

preserving contents of the memory;

updating the NVM from the memory;

resetting the processor by enabling a cold reboot; and

wherein the plurality of conditions include:

a warm reboot status;

an update request bit set in an ANVM coupled to the bus, the update request bit being indicative of a pending request to update the NVM from the memory; and

a checksum error status of the ANVM.

12. The system of claim 11 , wherein the instructions are substantially independent of a chipset included in the IHS.

13. The system of claim 11 , wherein the warm reboot status is determined by reading a predefined location in the memory and determining whether contents stored at the predefined location match predefined data.

14. The system of claim 11 further comprising:

a user interface coupled to the bus, wherein the user interface is provided prior to the updating; and

an output via the user interface, the output being indicative of a completion status of the updating.

15. The system of claim 12 , wherein a reset of the processor causes an execution of the instructions to update the NVM.