Semiconductor memory device and semiconductor memory device test method
View Patent ↗During writing of fail addresses to address registers, when writing of a number of fail addresses that is greater than the number of antifuses that have been provided in advance is about to be executed, or when a storage process of a number of fail addresses that is greater than the number of antifuses that have been provided in advance is about to be executed, delivering as output an overflow signal indicating that the writing or storage operation cannot be executed and reporting to the outside that remedy of defects by antifuses is no longer possible.
1. A semiconductor memory device comprising:
a plurality of antifuses, which are nonvolatile memory elements in which are stored fail addresses, said fail addresses being the addresses of memory cells in which defects have been detected;
a plurality of address registers provided to correspond to each of said antifuses for temporarily holding said fail addresses that are to be stored in said antifuses; and
an AF selection circuit for, during writing said fail addresses to said address registers, when writing of a number of said fail addresses that is greater than the number of said antifuses that have been provided in advance is to be executed, delivering as output an overflow signal indicating that the write operation cannot be executed.
2. The semiconductor memory device according to claim 1 , wherein:
“used” flags indicating that said fail addresses have already been stored in said antifuses are stored in said antifuses; and
based on said “used” flags, said AF selection circuit generates selection signals for selecting still unused antifuses and address registers as the storage destination of the fail address of a memory cell in which a defect is next detected.
3. The semiconductor memory device according to claim 1 , further including an output buffer for, during normal operation, supplying data that are read from said memory cells to the outside from a DQ terminal, which is the external input/output terminal of said data; and during testing of the semiconductor memory device, supplying said overflow signal to the outside from said DQ terminal.
4. A semiconductor memory device comprising:
a plurality of antifuses, which are nonvolatile memory elements in which are stored fail addresses, these fail addresses being addresses of memory cells in which defects have been detected;
a plurality of address registers provided to correspond to each of said antifuses for temporarily holding said fail addresses that are to be stored in said antifuses; and
an AF selection circuit for, during storage of said fail address in said antifuses, when a storage process of a number of said fail addresses that is greater than the number of said antifuses that have been provided in advance is to be executed, delivering as output an overflow signal indicating that the storage operation cannot be executed.
5. The semiconductor memory device according to claim 4 , wherein:
“used” flags indicating that said fail addresses have already been stored in said antifuses are stored in said antifuses; and
based on said “used” flags, said AF selection circuit generates selection signals for selecting still unused antifuses and address registers as the storage destination of the fail address of a memory cell in which a defect is next detected.
6. The semiconductor memory device according to claim 4 , further including an output buffer for, during normal operation, supplying data that are read from said memory cells to the outside from a DQ terminal, which is the external input/output terminal of said data; and during testing of the semiconductor memory device, supplying said overflow signal to the outside from said DQ terminal.
7. A semiconductor memory device test method for testing a semiconductor memory device, said semiconductor memory device including:
a plurality of antifuses, which are nonvolatile memory elements in which are stored fail addresses, said fail addresses being the addresses of memory cells in which defects have been detected; and
a plurality of address registers provided to correspond to each of said antifuses for temporarily holding said fail addresses that are to be stored in said antifuses;
said test method comprising the steps of:
causing output of an overflow signal from said semiconductor memory device when, during writing of said fail addresses to said address registers, writing of a number of said fail addresses that is greater than the number of said antifuses that have been provided in advance is to be executed, said overflow signal indicating that the writing cannot be executed; and
terminating a test upon detecting said overflow signal.
8. The semiconductor memory device test method according to claim 7 , wherein:
“used” flags indicating that said fail address have already been stored in said antifuses are stored in said antifuses; and
based on said “used” flags, selecting still unused antifuses and address registers as the storage destination of fail addresses of memory cells in which defects are next detected.
9. The semiconductor memory device test method according to claim 7 , wherein said overflow signal is supplied to the outside from a DQ terminal, which is an external input/output terminal for data.
10. A semiconductor memory device test method for testing a semiconductor memory device, said semiconductor memory device including:
a plurality of antifuses, which are nonvolatile memory elements in which are stored fail addresses, said fail addresses being the addresses of memory cells in which defects have been detected; and
a plurality of address registers provided to correspond to each of said antifuses for temporarily holding said fail addresses that are to be stored in said antifuses;
said test method comprising the steps of:
causing output of an overflow signal from said semiconductor memory device when, during storage of said fail addresses to said antifuses, a storage process of a number of said fail addresses that is greater than the number of said antifuses that have been provided in advance is to be executed, said overflow signal indicating that the storage process cannot be executed; and
terminating a test upon detecting said overflow signal.
11. The semiconductor memory device test method according to claim 10 , wherein:
“used” flags indicating that said fail address have already been stored in said antifuses are stored in said antifuses; and
based on said “used” flags, selecting still unused antifuses and address registers as the storage destination of fail addresses of memory cells in which defects are next detected.
12. The semiconductor memory device test method according to claim 10 , wherein said overflow signal is supplied to the outside from a DQ terminal, which is an external input/output terminal for data.