IP Library Patent Application 11377425
Patent Application
App. No. 11/377,425

Ball grid array package and process for manufacturing same

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Quick Facts
Patent No.
US None
App. No.
11/377,425
Abstract

A ball grid array integrated circuit package is manufactured by mounting a semiconductor die, to a first surface of a substrate such that bumps on the semiconductor die are electrically connected to conductive traces of the substrate. At least one collapsible spacer is mounted to at least one of a heat spreader, the semiconductor die and the substrate. The heat spreader is fixed to the at least one of the first surface of the substrate and the semiconductor die such that the at least one collapsible spacer is disposed therebetween. A ball grid array is formed on a second surface of the substrate, bumps of the ball grid array being electrically connected to the conductive traces and the integrated circuit package is singulated.

Claims (15)

1 .- 30 . (canceled)

31 . An integrated circuit package comprising:

a substrate having a plurality of conductive traces;

a semiconductor die flip-chip mounted to a first surface of said substrate, bumps of said semiconductor die being electrically connected to said ones of said plurality of conductive traces;

a heat spreader fixed to both said semiconductor die and said substrate by a plurality of collapsible spacers, one of said collapsible spacers disposed between and in contact with said heat spreader and said semiconductor die and further ones of said collapsible spacers disposed between and in contact with said heat spreader and said substrate; and

a ball grid array on a second surface of said substrate, bumps of said ball grid array being electrically connected to said conductive traces; and

a molding compound encapsulating the semiconductor die and said collapsible spacers between the substrate and the heat spreader.

32 . The integrated circuit package according to claim 31 , further comprising an underfill material disposed between said semiconductor die and said substrate.

33 . An integrated circuit package comprising:

a substrate having a plurality of conductive traces;

a semiconductor die flip-chip mounted to a first surface of said substrate, bumps of said semiconductor die being electrically connected to said ones of said plurality of conductive traces;

a heat spreader fixed to both said semiconductor die and said substrate by a plurality of collapsible spacers, one of said collapsible spacers disposed between and in contact with said heat spreader and said semiconductor die and further ones of said collapsible spacers disposed between and in contact with said heat spreader and said substrate; and

a ball grid array on a second surface of said substrate, bumps of said ball grid array being electrically connected to said conductive traces, wherein said collapsible spacers comprise one of solder and a thermoplastic; and

a molding compound encapsulating the semiconductor die and said collapsible spacers between the substrate and the heat spreader.

34 . The integrated circuit package according to claim 33 , further comprising an underfill material disposed between said semiconductor die and said substrate.

Assignments (5)
CHANGE OF NAME Recorded Oct 29, 2010
From: ASAT LIMITED
To: UTAC HONG KONG LIMITED
Reel/Frame 025221/0808 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS - FIRST PRIORITY Recorded Jun 29, 2010
From: UTAC HONG KONG LIMITED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024599/0743 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS - SECOND PRIORITY Recorded Jun 29, 2010
From: UTAC HONG KONG LIMITED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024599/0827 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS - SECOND PRIORITY Recorded Jun 29, 2010
From: UTAC HONG KONG LIMITED
To: THE HONGKONG AND SHANGHAI BANKING CORPORATION LIMITED, AS SECURITY AGENT
Reel/Frame 024611/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2006
From: KIRLOSKAR, MOHAN; FAN, CHUN HO; MCLELLAN, NEIL
To: ASAT LTD.
Reel/Frame 017701/0882 →