Graphical presentation of semiconductor test results
Methods and apparatus for graphically presenting test results of a circuit device under test are presented. Test results of a circuit device under test are acquired. Graphical diagrams comprising representations of at least a portion of the circuit device under test and having circuit components and associated circuit component terminals are generated with test results for nodes of the circuit device under test mapped to circuit component terminals of the displayed diagrams.
1 . A method for graphically presenting test results of a circuit device under test, the method comprising:
acquiring test results for corresponding circuit device nodes of the circuit device under test;
accessing a graphical diagram comprising a representation of at least a portion of the circuit device under test, the representation comprising a circuit component and associated circuit component terminals;
mapping the circuit component terminals represented in the graphical diagram to corresponding circuit device nodes of the circuit device under test; and
displaying the graphical diagram, enabling display of the test results corresponding to the circuit device nodes mapped to the circuit component terminals represented in the graphical diagram.
2 . The method of claim 1 , wherein the test results corresponding to the circuit device nodes mapped to the circuit component terminals represented in the graphical diagram are displayed in the representation of the circuit component and associated circuit component terminals.
3 . The method of claim 1 , wherein the step for displaying the graphical diagram comprises displaying for each respective circuit component terminal a bargraph representing the test results corresponding to the circuit device node that is mapped to the respective circuit component terminal.
4 . The method of claim 1 , wherein the step for displaying the graphical diagram comprises displaying for each respective circuit component terminal a color representing a number of failures detected on the corresponding circuit device node that is mapped to the respective circuit component terminal.
5 . The method of claim 1 , wherein the graphical diagram comprises a package layout representation of the component.
6 . The method of claim 5 , wherein the package layout representation comprises a bargraph representing the test results corresponding to the circuit device node that is mapped to the respective circuit component terminal.
7 . The method of claim 1 , wherein the step for enabling display of the test results corresponding to the circuit device nodes mapped to the circuit component terminals represented in the graphical diagram comprises providing a selection mechanism associated with the circuit component terminal represented in the graphical diagram that, when selected, display the test results corresponding to the circuit device node mapped to the selected circuit component terminal.
8 . The method of claim 1 , wherein the step for displaying the graphical image comprises providing a selection mechanism associated with the circuit component represented in the graphical diagram that, when selected, displays a functional diagram of the selected circuit component.
9 . A computer readable storage medium tangibly embodying program instructions implementing a method for graphically presenting test results of a circuit device under test, the method comprising:
acquiring test results for corresponding circuit device nodes of the circuit device under test;
accessing a graphical diagram comprising a representation of at least a portion of the circuit device under test, the representation comprising a circuit component and associated circuit component terminals;
mapping the circuit component terminals represented in the graphical diagram to corresponding circuit device nodes of the circuit device under test; and
displaying the graphical diagram, enabling display of the test results corresponding to the circuit device nodes mapped to the circuit component terminals represented in the graphical diagram.
10 . The computer readable storage medium of claim 9 , wherein the test results corresponding to the circuit device nodes mapped to the circuit component terminals represented in the graphical diagram are displayed in the representation of the circuit component and associated circuit component terminals.
11 . The computer readable storage medium of claim 9 , wherein the step for displaying the graphical diagram comprises displaying for each respective circuit component terminal a bargraph representing the test results corresponding to the circuit device node that is mapped to the respective circuit component terminal.
12 . The computer readable storage medium of claim 9 , wherein the step for displaying the graphical diagram comprises displaying for each respective circuit component terminal a color representing a number of failures detected on the corresponding circuit device node that is mapped to the respective circuit component terminal.
13 . The computer readable storage medium of claim 9 , wherein the graphical diagram comprises a package layout representation of the component.
14 . The computer readable storage medium of claim 13 , wherein the package layout representation comprises a bargraph representing the test results corresponding to the circuit device node that is mapped to the respective circuit component terminal.
15 . The computer readable storage medium of claim 9 , wherein the step for enabling display of the test results corresponding to the circuit device nodes mapped to the circuit component terminals represented in the graphical diagram comprises providing a selection mechanism associated with the circuit component terminal represented in the graphical diagram that, when selected, display the test results corresponding to the circuit device node mapped to the selected circuit component terminal.
16 . The computer readable storage medium of claim 9 , wherein the step for displaying the graphical image comprises providing a selection mechanism associated with the circuit component represented in the graphical diagram that, when selected, displays a functional diagram of the selected circuit component.
17 . A circuit test results analysis system, comprising:
test results receiving means for receiving test results for corresponding circuit device nodes of a circuit device under test;
graphical diagram generation means for accessing a graphical diagram comprising a representation of at least a portion of the circuit device under test, the representation comprising a circuit component and associated circuit component terminals, mapping the circuit component terminals represented in the graphical diagram to corresponding circuit device nodes of the circuit device under test, and displaying the graphical diagram, enabling display of the test results corresponding to the circuit device nodes mapped to the circuit component terminals represented in the graphical diagram.
18 . The system of claim 17 , wherein graphical diagram generation means displays the test results corresponding to the circuit device nodes mapped to the circuit component terminals represented in the graphical diagram.
19 . The system of claim 17 , wherein graphical diagram generation means generates and displays, for each respective circuit component terminal, a bargraph representing the test results corresponding to the circuit device node that is mapped to the respective circuit component terminal.
20 . The system of claim 17 , wherein graphical diagram generation means generates and displays, for each respective circuit component and respective circuit component terminal having available expanded information, a selection mechanism associated with the respective circuit component and respective circuit component terminal represented in the graphical diagram that, when selected, displays the available expanded information corresponding to the respective circuit component or respective circuit component terminal.